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SM802105UMG Arkusz danych(PDF) 6 Page - Micrel Semiconductor |
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SM802105UMG Arkusz danych(HTML) 6 Page - Micrel Semiconductor |
6 / 11 page Micrel, Inc. SM802105 April 2011 6 M9999-042111-A hbwhelp@micrel.com or (408) 955-1690 AC Electrical Characteristics (4, 5) VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5% VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5% TA = −40°C to +85°C. RL = 50Ω to VDDO − 2V Symbol Parameter Condition Min. Typ. Max. Units FOUT1 Output Frequency 1 FSEL=1 156.25 MHz FOUT2 Output Frequency 2 FSEL=0 312.5 MHz Ppm Output ppm Variation Crystal reference. Note 6 −50 50 ppm FREF Reference Input Frequency 25 MHz TR/TF LVPECL Output Rise/Fall Time 20% – 80% 80 175 350 ps ODC Output Duty Cycle 48 50 52 % TSKEW Output-to-Output Skew Within bank. Note 7 45 ps TLOCK PLL Lock Time 20 ms Tjit(∅) RMS Phase Jitter (8) 156.25MHz Integration Range (1.875MHz – 20MHz) Integration Range (12kHz – 20MHz) 312.5MHz Integration Range (1.875MHz – 20MHz) Integration Range (12kHz – 20MHz) 110 250 110 250 fs Spurious Noise Components 6.25MHz using 156.25MHz 12.5MHz using 312.5MHz -80 -85 dBc Notes: 5. All phase noise measurements were taken with an Agilent 5052B phase noise system. 6. Crystal tolerance at room less than ± 15ppm, over temp less than ±20ppm. 7. Defined as skew between outputs at the same supply voltage and with equal load conditions and same frequency; Measured at the output differential crossing points. 8. Measured using 25MHz crystal as the input reference source. If using an external reference input, use a low phase noise source. With an external reference, the phase noise will follow the input source phase noise up to about 1MHz. |
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