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FQPF13N50C Arkusz danych(PDF) 5 Page - Fairchild Semiconductor |
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FQPF13N50C Arkusz danych(HTML) 5 Page - Fairchild Semiconductor |
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5 / 15 page  AN-6982 APPLICATION NOTE © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.0 • 6/8/10 5 Soft-Start Function The soft-start is combined with RDY pin operation. During startup, the RDY pin remains floating until the PFC output voltage reaches 96% of its nominal value. When the supply voltage of the downstream converter is controlled by the RDY pin, the PFC stage starts with no load since the downstream converter does not operate until the PFC output voltage is built to a certain level. Usually the error amplifier output VEA is saturated to HIGH during the startup since the actual output voltage is less than the target value. VEA remains saturated to HIGH until the PFC output voltage reaches its target value. Once the PFC output reaches its target value, the error amplifier comes out of saturation. However, it takes several line cycles for VEA to drop to its proper value for the output regulation, which delivers more power to the load than required, causing output voltage overshoot. To prevent output voltage overshoot during startup caused by the saturation of error amplifier; FAN6982 clamps the error amplifier output voltage (VEA) at 2.8V, which is half of its maximum value, until PFC output reaches 96% of its nominal value. Once the PFC output voltage reaches 96% of its nominal value, the clamping function of VEA is disabled. Then the voltage of PFC output is regulated by voltage control loop. Nominal Output Voltage 96% of Nominal Output Voltage 2.8V VEA VOUT VEA SAT VDD of Downstream DC/DC Input Line Current Figure 12. PFC Soft-Start |
Podobny numer części - FQPF13N50C |
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