Zakładka z wyszukiwarką danych komponentów |
|
FFPF10H60S Arkusz danych(PDF) 10 Page - Fairchild Semiconductor |
|
FFPF10H60S Arkusz danych(HTML) 10 Page - Fairchild Semiconductor |
10 / 15 page AN-6982 APPLICATION NOTE © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.0 • 6/8/10 10 [STEP-6] PFC Current-Sensing Circuit Design Figure 18 shows the PFC compensation circuits for the input current shaping and output voltage regulation. The first step in compensation network design is to select the current-sensing resistor of PFC converter considering the maximum power limit. Since line feed-forward is used, the output power is proportional to the voltage control error amplifier voltage as: 0.6 () 0.6 MAX EA OUT EA OUT SAT EA V PV P V − =⋅ − (26) where VEA SAT is 5.6V and the maximum power limit of PFC given by the maximum VEA voltage is: 2 . MAX MAX LINE BO M OUT IAC CS VG R P RR ⋅⋅ = (27) where RM is internal modulator resistor whose typical value is 5.7kΩ, RIAC is a resistor connected between IAC pin, and PFC input and GMAX is the maximum of ratio of IAC pin current and modulator output current (IMO/IAC). The typical value of GMAX is 9 when VRMS pin voltage is 1.05V, which is related to the brownout protection threshold of line voltage (VLINE.BO). It is typical to set the maximum power limit of the PFC stage around 1.2~1.5 of its nominal output power, such that the VEA is around 4~4.5V at nominal output power. By adjusting the current-sensing resistor for the PFC converter, the maximum power limit of the PFC stage can be programmed. To filter out the current ripple of switching frequency, an RC filter is typically used for the ISENSE pin. RLF should not be larger than 100Ω and the time constant of the filter should be 300~500ns to properly remove the leading-edge current spike caused by reverse recovery of output diode. Diodes D1 and D2 are required to prevent over-voltage on the ISENSE pin due to the inrush current that might damage FAN6982. A fast recovery diode or ultra-fast recovery diode is recommended. Figure 18. Gain Modulation Block (Design Example) Setting the maximum power limit of the PFC stage as 450W (around 130% of nominal output power), the current sensing resistor is obtained as: 2 23 . 6 72 9 5.7 10 0.098 6 10 450 ⋅⋅ ⋅⋅ × = == Ω ×⋅ MAX LINE BO M CS MAX IAC BOUT VG R R RP Thus, 0.1 Ω resistor is selected. [STEP-8] PFC Current Loop Design The transfer function from duty cycle to the inductor current of boost power stage is given as: = ) ) BOUT L BOOST V i sL d (28) The transfer function from the output of the current control error amplifier to the inductor current-sensing voltage is obtained as: ⋅ = ⋅ ) ) CS CS BOUT IEA RAMP BOOST vR V vV sL (29) where VRAMP is the peak to peak voltage of ramp signal for current control PWM comparator, which is 2.55V. The transfer function of the compensation circuit is given as: 1 2 2 1 2 π π π + =⋅ + ) ) IC IEA II CS IP s f vf s vs f (30) |
Podobny numer części - FFPF10H60S |
|
Podobny opis - FFPF10H60S |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |