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FAN3224CMPX Arkusz danych(PDF) 3 Page - Fairchild Semiconductor

Numer części FAN3224CMPX
Szczegółowy opis  Dual 4A High-Speed, Low-Side Gate Drivers
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Producent  FAIRCHILD [Fairchild Semiconductor]
Strona internetowa  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN3224CMPX Arkusz danych(HTML) 3 Page - Fairchild Semiconductor

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© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.6
3
FAN3223
FAN3224
FAN3225
Figure 4. Pin Assignments (Repeated)
Pin Definitions
Name
Pin Description
ENA
Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and
CMOS INx threshold.
ENB
Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and
CMOS INx threshold.
GND
Ground. Common ground reference for input and output circuits.
INA
Input to Channel A.
INA+
Non-Inverting Input to Channel A. Connect to VDD to enable output.
INA-
Inverting Input to Channel A. Connect to GND to enable output.
INB
Input to Channel B.
INB+
Non-Inverting Input to Channel B. Connect to VDD to enable output.
INB-
Inverting Input to Channel B. Connect to GND to enable output.
OUTA
Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
OUTB
Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
OUTA
Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is
above UVLO threshold.
OUTB
Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is
above UVLO threshold.
P1
Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected
to GND; NOT suitable for carrying current.
VDD
Supply Voltage. Provides power to the IC.
Output Logic
FAN3223 (x=A or B)
FAN3224 (x=A or B)
FAN3225 (x=A or B)
ENx
INx
OUTx
ENx
INx
OUTx
INx+
INx−
OUTx
0
0
0
0
0
(7)
0
0
(7)
0
0
0
1
(7)
0
0
1
0
0
(7)
1
(7)
0
1
(7)
0
1
1
(7)
0
(7)
0
1
0
1
1
(7)
1
(7)
0
1
(7)
1
1
1
1
(7)
0
Note:
7.
Default input signal if no external connection is made.


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