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KA7500CDTF Arkusz danych(PDF) 7 Page - Fairchild Semiconductor |
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KA7500CDTF Arkusz danych(HTML) 7 Page - Fairchild Semiconductor |
7 / 8 page © 2003 Fairchild Semiconductor Corporation www.fairchildsemi.com KA7500C • Rev. 1.0.2 7 Physical Dimensions 16 9 8 1 NOTES: UNLESS OTHERWISE SPECIFIED A THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BB B) ALL DIMENSIONS ARE IN MILLIMETERS. D) CONFORMS TO ASME Y14.5M-1994 E) DRAWING FILE NAME: N16EREV1 19.68 18.66 6.60 6.09 C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR PROTRUSIONS 3.42 3.17 3.81 2.92 (0.40) 2.54 17.78 0.58 0.35 1.78 1.14 5.33 MAX 0.38 MIN 8.13 7.62 0.35 0.20 15 0 8.69 A A TOP VIEW SIDE VIEW Figure 4. 16-Lead Dual Inline Package (DIP Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. |
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