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3N166_TO-78 Arkusz danych(PDF) 1 Page - Micross Components

Numer części 3N166_TO-78
Szczegółowy opis  a monolithic dual enhancement mode P-Channel Mosfet
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Producent  MICROSS [Micross Components]
Strona internetowa  http://www.micross.com
Logo MICROSS - Micross Components

3N166_TO-78 Arkusz danych(HTML) 1 Page - Micross Components

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Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
FEATURES 
DIRECT REPLACEMENT FOR INTERSIL 3N166 
ABSOLUTE MAXIMUM RATINGS
1@ 25°C (unless otherwise noted) 
Maximum Temperatures 
Storage Temperature ‐65°C to +200°C 
Operating Junction Temperature ‐55°C to +150°C 
Lead Temperature (Soldering, 10 sec.) 
+300°C 
Maximum Power Dissipation 
Continuous Power Dissipation (one side) 
300mW 
Total Derating above 25°C
4.2 mW/°C 
MAXIMUM CURRENT
Drain Current 
50mA 
MAXIMUM VOLTAGES 
Drain to Gate or Drain to Source
2 ‐30V 
Peak Gate to Source
3
±125V 
Gate‐Gate Voltage 
±80V 
3N166 ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL 
CHARACTERISTIC 
MIN 
TYP. 
MAX 
UNITS 
CONDITIONS 
IGSSR 
Gate Reverse Leakage Current 
‐‐ 
‐‐ 
10  
 
pA 
VGS = ‐0V 
IGSSF 
Gate Forward Current  
‐‐ 
‐‐ 
‐10 
VGS = ‐40V 
 
TA= +125°C 
‐‐ 
‐‐ 
‐25 
IDSS 
Drain to Source Leakage Current 
‐‐ 
‐‐ 
‐200 
VDS = ‐20V 
ISDS 
Source to Drain Leakage Current 
‐‐ 
‐‐ 
‐400 
VSD = ‐20V  VDB = 0 
ID(on) 
Drain Current “On” ‐5.0 
‐‐ 
‐30 
mA 
VDS = ‐15V,  VGS = ‐10V 
VGS(th) 
Gate to Source Threshold Voltage ‐2.0 
‐‐ 
‐5.0 
VDS = ‐15V,   I= ‐10µA 
‐2.0 
‐‐ 
‐5.0 
VDS =  VGS ,   ID = ‐10µA 
rDS(on) 
Drain to Source “On” Resistance 
‐‐ 
‐‐ 
300 Ω 
VGS = ‐20V,   ID = ‐100µA 
gfs 
Forward Transconductance 
1500 
‐‐ 
3000 
µS 
VDS = ‐15V,    ID = ‐10mA ,   f = 1kHz 
gos 
Output Admittance 
‐‐ 
‐‐ 
300 
Ciss  Input Capacitance 
‐‐ 
‐‐ 
3  
pF 
 
VDS = ‐15V,    ID = ‐10mA ,   f = 1MHz
4 
Crss 
Reverse Transfer Capacitance 
‐‐ 
‐‐ 
0.7 
Coss 
Output Capacitance 
‐‐ 
‐‐ 
3.0 
RE(Yfs
Common Source Forward 
Transconductance 
1200 
‐‐ 
‐‐ 
µS 
VDS = ‐15V,    I= ‐10mA ,   f = 100MHz
4 
MATCHING CHARACTERISTICS 3N166                                                                                                                                      
SYMBOL 
CHARACTERISTIC 
LIMITS  
UNITS 
 
CONDITIONS 
MIN 
MAX 
Yfs1/Yfs2  
Forward Transconductance Ratio 
0.90 
1.0 
ns 
VDS = ‐15V,    I= ‐500µA ,   f = MHz
4 
VGS1‐2 
Gate Source Threshold Voltage 
Differential 
‐‐ 
100 
mV 
VDS = ‐15V,    I= ‐500µA 
∆VGS1‐2/∆T 
Gate Source Threshold Voltage 
Differential Change with Temperature 
‐‐ 
100 
µV/°C 
VDS = ‐15V,    I= ‐500µA 
T= ‐55°C to = +25°C 
 
 
  
                                  SWITCHING TEST CIRCUIT 
The 3N166 is a monolithic dual enhancement mode P-Channel Mosfet
3N166
P-CHANNEL MOSFET
Note 1 ‐ Absolute maximum ratings are limiting values above which 3N166 serviceability may be impaired. *
Note 2 – Per Transistor 
Note 3 – Device must not be tested at ±125V more than once or longer than 300ms. 
Note 4 – For design reference only, not 100% tested
The 3N166 is a dual enhancement mode P-Channel
Mosfet and is ideal for space constrained applications
and those requiring tight electrical matching.
The hermetically sealed TO-78 package is well suited
for high reliability and harsh environment applications.
(See Packaging Information).
Tel: +44 1603 788967
Email: chipcomponents@micross.com
Web: http://www.micross.com/distribution
Device Schematic
TO-78 (Bottom View)
Available Packages:
3N166 in TO-72
3N166 in bare die.
Please contact Micross for full
package and die dimensions
3N166 Features:
Very high Input Impedance
Low Capacitance
High Gain
High Gate Breakdown Voltage
Low Threshold Voltage
SWITCHING WAVEFORM & TEST CIRCUIT
*To avoid possible damage to the device while wiring, testing, or in actual 
operation, follow these procedures: To avoid the build‐up of static charge, the 
leads of the devices should remain shorted together with a metal ring except 
when being tested or used. Avoid unnecessary handling. Pick up devices by the 
case instead of the leads. Do not insert or remove devices from circuits with the 
power on, as transient voltages may cause permanant damage to the devices. 


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