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AD9484 Arkusz danych(PDF) 5 Page - Analog Devices |
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AD9484 Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 24 page AD9484 Rev. A | Page 5 of 24 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 3. Parameter1 Temp Min Typ Max Unit CLOCK INPUTS Logic Compliance Full CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage High Level Input (VIH) Full 0.2 1.8 V p-p Low Level Input (VIL) Full −1.8 −0.2 V p-p High Level Input Current (IIH) Full −10 +10 μA Low Level Input Current (IIL) Full −10 +10 μA Input Resistance (Differential) Full 8 10 12 kΩ Input Capacitance Full 4 pF LOGIC INPUTS Logic 1 Voltage Full 0.8 × DRVDD V Logic 0 Voltage Full 0.2 × DRVDD V Logic 1 Input Current (SDIO, CSB) Full 0 μA Logic 0 Input Current (SDIO, CSB) Full −60 μA Logic 1 Input Current (SCLK, PDWN) Full 50 μA Logic 0 Input Current (SCLK, PDWN) Full 0 μA Input Capacitance Full 4 pF LOGIC OUTPUTS2 VOD Differential Output Voltage Full 247 454 mV VOS Output Offset Voltage Full 1.125 1.375 V Output Coding 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 LVDS RTERMINATION = 100 Ω. |
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