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AD9643BCPZRL7-250 Arkusz danych(PDF) 8 Page - Analog Devices |
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AD9643BCPZRL7-250 Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 36 page AD9643 Rev. A | Page 8 of 36 SWITCHING SPECIFICATIONS Table 4. AD9643-170 AD9643-210 AD9643-250 Parameter Temp Min Typ Max Max Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz Conversion Rate1 Full 40 170 40 210 40 250 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 5.8 4.8 4 ns CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns Divide-by-2 Mode Through Divide-by-8 Mode Full 0.8 0.8 0.8 ns Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms DATA OUTPUT PARAMETERS LVDS Mode Data Propagation Delay (tPD) Full 4.8 4.8 4.8 ns DCO Propagation Delay (tDCO) Full 5.5 5.5 5.5 ns DCO-to-Data Skew (tSKEW) Full 0.1 0.7 1.3 0.1 0.7 1.3 0.1 0.7 1.3 ns Pipeline Delay (Latency) Full 10 10 10 Cycles Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms Wake-Up Time (from Standby) Full 10 10 10 μs Wake-Up Time (from Power-Down) Full 250 250 250 μs Out-of-Range Recovery Time Full 3 3 3 Cycles 1 Conversion rate is the clock rate after the divider. |
Podobny numer części - AD9643BCPZRL7-250 |
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Podobny opis - AD9643BCPZRL7-250 |
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