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ISL29028A_1103 Arkusz danych(PDF) 8 Page - Intersil Corporation

Numer części ISL29028A_1103
Szczegółowy opis  Low Power Ambient Light and Proximity Sensor with Intelligent Interrupt and Sleep Modes
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Producent  INTERSIL [Intersil Corporation]
Strona internetowa  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL29028A_1103 Arkusz danych(HTML) 8 Page - Intersil Corporation

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ISL29028A
8
FN7721.2
March 24, 2011
Principles of Operation
I2C Interface
The ISL29028A’s I2C interface slave address is internally hardwired
as 0b100010<x>, where “0b” signifies binary notation and x
represents the logic level on pin ADDR0.
Figure 2 shows a sample one-byte read. The I2C bus master
always drives the SCL (clock) line, while either the master or the
slave can drive the SDA (data) line. Every I2C transaction begins
with the master asserting a start condition (SDA falling while SCL
remains high). The first transmitted byte is initiated by the
master and includes 7 address bits and a R/W bit. The slave is
responsible for pulling SDA low during the ACK bit after every
transmitted byte.
Each I2C transaction ends with the master asserting a stop
condition (SDA rising while SCL remains high).
For more information about the I2C standard, please consult the
Philips™ I2C specification documents.
Photodiodes and ADCs
The ISL29028A contains two photodiode arrays which convert
photons (light) into current. The ALS photodiodes are constructed to
mimic the human eye’s wavelength response curve to visible light
(see Figure 6). The ALS photodiodes’ current output is digitized by a
12-bit ADC in 100ms. These 12 bits can be accessed by reading
from I2C registers 0x9 and 0xA when the ADC conversion is
completed.
The ALS converter is a charge-balancing integrating 12-bit ADC.
Charge-balancing is best for converting small current signals in the
presence of periodic AC noise. Integrating over 100ms highly rejects
both 50Hz and 60Hz light flicker by picking the lowest integer
number of cycles for both 50Hz/60Hz frequencies.
TABLE 11. REGISTER 0x09 (ALSIR_DT1) - ALS/IR SENSOR DATA (LOWER 8 BITS)
BIT #
ACCESS
DEFAULT
BIT NAME
FUNCTION/OPERATION
7:0
RO
0x00
ALSIR_DATA
(ALS/IR Data)
Lower 8 bits (of 12 bits) from result of ALS/IR sensor conversion
TABLE 12. REGISTER 0x0A (ALSIR_DT2) - ALS/IR SENSOR DATA (UPPER 4 BITS)
BIT #
ACCESS
DEFAULT
BIT NAME
FUNCTION/OPERATION
7:4
RO
0x00
(Unused)
Unused bits
3:0
RO
0x00
ALSIR_DATA
(ALS/IR Data)
Upper 4 bits (of 12 bits) from result of ALS/IR sensor conversion
TABLE 13. REGISTER 0x0E (TEST1) - TEST MODE
BIT #
ACCESS
DEFAULT
BIT NAME
FUNCTION/OPERATION
7:0
RW
0x00
(Write as 0x00)
Test mode register. When 0x00, in normal operation
TABLE 14. REGISTER 0x0F (TEST2) - TEST MODE 2
BIT #
ACCESS
DEFAULT
BIT NAME
FUNCTION/OPERATION
7:0
RW
0x00
(Write as 0x00)
Test mode register. When 0x00, in normal operation
FIGURE 2. I2C DRIVER TIMING DIAGRAM FOR MASTER AND SLAVE CONNECTED TO COMMON BUS
START
W A
A
A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A
A6 A5 A4 A3 A2 A1 A0 W A
A
A
A D7 D6 D5 D4 D3D2 D1D0
13
5
7
13
57
12 3
4 5
6
9
2
4
6
STOP START
SDA DRIVEN BY MASTER
DEVICE ADDRESS
SDA DRIVEN BY ISL29028A
DATA BYTE0
REGISTER ADDRESS
SLAVE
DEVICE ADDRESS
I2C DATA
SDA DRIVEN BY MASTER
SDA DRIVEN BY MASTER
24
68 9
2
468 9
7
8
1
357 8
9
I2C SDA
I2C SDA
I2C CLK
MASTER
(ISL29028A)


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