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74LVC2G34GN Arkusz danych(PDF) 6 Page - NXP Semiconductors |
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74LVC2G34GN Arkusz danych(HTML) 6 Page - NXP Semiconductors |
6 / 17 page 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 6 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate 11. Dynamic characteristics [1] Typical values are measured at Tamb =25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(C L × VCC2 × fo) = sum of outputs. 12. Waveforms Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 8. Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max tpd propagation delay nA to nY; see Figure 7 [2] VCC = 1.65 V to 1.95 V 1.0 3.8 8.6 1.0 10.8 ns VCC = 2.3 V to 2.7 V 0.5 2.4 4.4 0.5 5.5 ns VCC = 2.7 V 0.5 2.5 5.0 0.5 6.3 ns VCC = 3.0 V to 3.6 V 0.5 2.2 4.1 0.5 5.1 ns VCC = 4.5 V to 5.5 V 0.5 1.9 3.2 0.5 4.0 ns CPD power dissipation capacitance VI = GND to VCC; VCC = 3.3 V [3] -20- - - pF Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The data input (nA) to output (nY) propagation delays mnb072 nA input nY output tPLH tPHL GND VI VM VM VM VM VOH VOL |
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