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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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GS1503BCVE2 Arkusz danych(PDF) 7 Page - Gennum Corporation |
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GS1503BCVE2 Arkusz danych(HTML) 7 Page - Gennum Corporation |
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7 / 90 page  GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 7 of 90 16, 18, 20, 36, 48, 56, 64, 72, 80, 86, 88, 108, 113, 121, 129, 144 GND – Device ground. 17 ACLKA I Input audio signal clock at 6.144 MHz (128 fs) for channels 1 to 4. 19 ACLKB I Input audio signal clock at 6.144 MHz (128 fs) for channels 5 to 8. 21 ERROR O Format error indicator. When HIGH, the incoming video data stream contains TRS errors or there are errors within the incoming ancillary data packets. 22 OPERATE O Audio processing indicator. When HIGH, audio data is being multiplexed or demultiplexed. 23 CRC_ERROR O CRC error indicator. Will be set HIGH when a CRC error is detected in the incoming video data stream. 24 PKTENO O Arbitrary data packet timing signal. Valid in Multiplex Mode only. Will be HIGH when arbitrary data packets can be input to the device. This signal is only valid when multiplexing arbitrary data packets via the PKT[7:0] bus. See Figure 4-22 for timing. 25 PKTEN I/O Arbitrary data packet enable. In Multiplex Mode, PKTEN is an input and must be set HIGH two VCLK cycles after the PKTENO signal goes HIGH. Arbitrary packet data is input to the device two VCLK cycles after PKTEN is set HIGH. In Demultiplex Mode, PKTEN is an output and is set HIGH two VCLK cycles before the device outputs arbitrary packet data. See Figure 4-22 and Figure 5-12. 26, 28, 29, 30, 32, 33, 34, 35 PKT[7:0] I/O Arbitrary data I/O bus. PKT[7] is the MSB and PKT[0] is the LSB. In Multiplex Mode, the user must input the arbitrary data packet words starting from the data identification (DID) to the last user data word (UDW) according to SMPTE 291M. The GS1503B internally converts the data to 10 bits by generating the parity bit (bit 8) and inversion bit (bit 9). The checksum (CS) word is also generated internally. In Demultiplex Mode, the GS9023 outputs the arbitrary data packet words starting from the DID to the last UDW. See Figure 4-22 and Figure 5-12. 38 SCRBYPASS I Scrambler bypass. When set LOW, the output video stream is scrambled according to SMPTE 292M and NRZ(I) encoded. When set HIGH, the scrambler and NRZ(I) encoder are bypassed. 39, 40, 41, 42 RSV – Connect to ground. 43 EXTH I/O Horizontal sync signal. The GS1503B outputs a horizontal sync signal derived from the incoming TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a horizontal sync signal can be input to the device for TRS and line number insertion. 44 EXTF I/O Field sync signal. The GS1503B outputs a field sync signal derived from the incoming TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a field sync signal can be input to the device for TRS and line number insertion. For progressive formats, a signal with a high to low transition at the position of line one must be provided. See Figure 4-6 and Figure 4-7. 45 VIDEO_DET O Video input signal detection. Indicates that the device has detected a valid video input stream. NOTE: When EXT_SEL is set HIGH in the Host Interface, VIDEO_DET will indicate when valid EXTH and EXTF signals have been detected. Table 1-1: Pin Descriptions (Continued) Number Symbol Type Description |
Podobny numer części - GS1503BCVE2 |
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Podobny opis - GS1503BCVE2 |
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