GS4915_09 datasheet(6/27 Pages) GENNUM

Numer części	GS4915

Szczegółowy opis	ClockCleaner

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GS4915 ClockCleaner™

Data Sheet

39145 - 5

June 2009

6 of 27

1.2 Pin Descriptions

Table 1-1: Pin Descriptions

Number

Name

Timing

Type

Description

1

REG_VDD

–

Power

Positive power supply connection for the internal voltage regulator.

Connect to filtered +3.3V DC.

2, 6, 9, 26,

30, 31, 40

AGND

–

Power

Ground connection for analog blocks and IOs. Connect to clean analog

GND.

3

PD_VDD

–

Power

Positive power supply connection for the phase detector. Connect to

filtered +1.8V DC.

4, 5

CLKIN, CLKIN

–

Input

CLOCK SIGNAL INPUTS

Signal levels are CML/LVDS compatible.

A differential clock input signal is applied to these pins.

7

IN_VDD

–

Power

Positive power supply connection for the single-ended and differential

input clock buffers. Supplies CLKIN_SE. Connect to filtered +1.8V DC.

8

CLKIN_SE

–

Input

CLOCK SIGNAL INPUT

Signal levels are LVCMOS compatible.

A single-ended video clock input signal is applied to this pin.

10

RESET

Non

synchronous

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

See Section 3.8.1 for operation.

11

IPSEL

Non

synchronous

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS compatible.

Selects which input clock is cleaned by the device.

See Section 3.2.3 for operation.

12, 20, 22

GND

–

Power

Ground connection for digital blocks and IO’s. Connect to GND.

13

BYPASS

Non

synchronous

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS compatible.

See Manual Bypass Section 3.4.2.

14

AUTOBYPASS

Non

synchronous

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS compatible.

Selects the bypass mode of the device.

See Manual Bypass Section 3.4.2.

15

D_VDD

–

Power

Positive power supply connection for digital block. Connect to filtered

+1.8V DC. The digital block includes pins 10 - 21.

17, 16

FCTRL1, FCTRL0

Non

synchronous

Input

CONTROL SIGNAL INPUTS

Signal levels are LVCMOS compatible.

Selects the frequency mode of the device.

See Section 3.4.1 for operation.

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