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GS4915 Arkusz danych(PDF) 11 Page - Gennum Corporation |
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GS4915 Arkusz danych(HTML) 11 Page - Gennum Corporation |
11 / 27 page GS4915 ClockCleaner™ Data Sheet 39145 - 5 June 2009 11 of 27 Output Jitter Differential Output – 100kHz to 10MHz – 20 – ps – – Unfiltered – 40 – ps – Output Jitter Single-ended Output – 100kHz to 10MHz – 60 – ps – – Unfiltered – 100 – ps – Output Duty Cycle – Differential output 45 – 55 % – Single-ended output 40 – 60 % – Differential Clock Output Rise / Fall Time – 100 Ω diff. load – 500 – ps – Single-ended Clock Output Rise / Fall Time – 10 pF load – 1200 – ps – Input Clock Frequency – – 12 – 165 MHz – Output Clock Frequency – – 12 – 165 MHz – Lock Detect Time tLOCKD Within 300ppm of reference frequency – – 500 us – Unlock Detect Time tUNLOCKD Within 700ppm of reference frequency – – 500 us – Lock Time tLOCK –– – 1 s 2 Device Latency – Differential in, Differential out, SKEW_EN = LOW –1.2 – ns – Differential in, Differential out, SKEW_EN = HIGH – 1.2 - Tout/4 –ns – Single ended in, single ended out, SKEW_EN = LOW –3.5 – ns – Single ended in, single ended out, SKEW_EN = HIGH – 3.5 - Tout/4 –ns – Device Latency Difference – – – 750 – ps 3 NOTES: 1. One UI refers to one cycle of the input CLK. 2. Assuming power up has already occurred. 3. Difference between cleaning and bypass modes. Table 2-2: AC Electrical Characteristics (Continued) VDD = 1.8V ±5%, TA = 0ºC to 70ºC, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Notes |
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