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FM25640C Arkusz danych(PDF) 5 Page - Ramtron International Corporation |
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FM25640C Arkusz danych(HTML) 5 Page - Ramtron International Corporation |
5 / 13 page FM25640C - 64Kb 5V SPI F-RAM Rev. 1.1 June 2011 5 of 13 Data Transfer All data transfers to and from the FM25640C occur in 8-bit groups. They are synchronized to the clock signal (SCK) and they transfer most significant bit (MSB) first. Serial inputs are registered on the rising edge of SCK. The SO output is driven from the falling edge of SCK. Command Structure There are six commands called op-codes that can be issued by the bus master to the FM25640C. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations. They perform a single function such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate on the status register. The third group includes commands for memory transactions followed by an address and one or more bytes of data. Table 1. Op-code Commands Name Description Op-code value WREN Set Write Enable Latch 0000_0110b WRDI Write Disable 0000_0100b RDSR Read Status Register 0000_0101b WRSR Write Status Register 0000_0001b READ Read Memory Data 0000_0011b WRITE Write Memory Data 0000_0010b WREN - Set Write Enable Latch The FM25640C will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the status register and writing the memory. Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the status register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the status register has no effect. Completing any write operation will automatically clear the write-enable latch and prevent further writes without another WREN command. Figure 5 illustrates the WREN command bus configuration. WRDI - Write Disable The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the status register and verifying that WEL=0. Figure 6 illustrates the WRDI command bus configuration. Figure 5. WREN Bus Configuration Figure 6. WRDI Bus Configuration |
Podobny numer części - FM25640C |
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Podobny opis - FM25640C |
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