LA6242H

No.7814-2/9

Recommended Operating Conditions at Ta = 25

°C

Parameter

Symbol

Conditions

Ratings

Unit

Supply voltage

VCC

5 to 13

V

Electrical Characteristics at Ta = 25°C,VCCS = VCCP1 = VCCP2 = 8 V, VREF = 2.5 V, MUTE = 5 V

Ratings

Parameter

Symbol

Conditions

min

typ

max

Unit

Overall

Quiescent current 1

ICC-ON

All channel outputs on, MUTE pin: high

30

45

mA

Quiescent current 2

ICC-OFF

All channel outputs off, MUTE pin: low

5

10

mA

Muting function on voltage

VMUTE-ON

MUTE

∗1

2

V

Muting function off voltage

VMUTE-OFF

MUTE

∗1

0.5

V

Thermal shutdown

TSD

*4

150

175

200

°C

BTL Amplifier

(Channel 1) (Output Amplifier Block)

Input amplifier offset voltage

VOFF_OP-AMP Channel 1, input operational amplifiers A and B

-50

+50

mV

Output voltage

VO1

RL = 8Ω ∗2

6.2

6.5

V

I/O gain

VG1

∗3

5.4

6

6.6

Times

Slew rate

SR1

With the amplifier operating independently, twice

the value measured between outputs

∗3,∗4

0.5

V/

µs

Input Operational Amplifier

Output offset voltage

VOFF1

Input operational amplifiers A and B

-10

+10

mV

OP-AMP_SINK

OP_SINK

Input operational amplifier sink current

2

mA

OP-AMP_SOURCE

OP_SOURCE

Input operational amplifier source current

300

500

µA

Input Operational Amplifier Switching

Input amplifier switching voltage 1

VIN1-SW

Channel 1, with input operational amplifier B

selected

∗5

0.5

V

Input amplifier switching voltage 2

VIN1-SW

Channel 1, with input operational amplifier A

selected

∗5

2

V

BTL Amplifier

(Channels 2 to 4) (Output Amplifier Block)

Output offset voltage

VOFF2

Between the

+ and - outputs for each channel

-50

+50

mV

Output voltage

VO2

RL = 8Ω, between the + and - outputs for each

channel

∗2

5

5.4

V

I/O gain

VG2

5.4

6

6.6

Multip

lier

Slew rate

SR2

Amplifier independently, twice the value

measured between outputs

∗3,∗4

0.5

V/

µs

Regulator Voltage

VREG output voltage

VREG

∗6

1.21

1.26

1.31

V

REG-IN sink current

REG-IN-SINK

The base current of the external PNP transistor

5

10

mA

Line regulation

∆VOLN

6V

≤ VCC ≤ 12V, IO = 200mA

20

150

mV

Load regulation

∆VOLD

5mA

≤ IO ≤ 200mA

50

200

mV

*1: When the MUTE pin is high, the outputs will be on, and when low, the outputs will be off. (In the amplifier output off state, the outputs are in the

high-impedance state.) This operation applies to all channels.

*2: The voltage across the load terminals when an 8

Ω load is connected across the outputs. With the input either high or low. With the output in the saturated

state.

*3: The channel 1 input operational amplifier has a 0dB gain, i.e. it is a buffer amplifier.

*4: Design guarantee value

*5: When VIN1-SW is high, operational amplifier A operates, and when low, operational amplifier B operates.

*6: For testing, short the REGOUT to the collector of the external PNP-transistor.