LC88F85D0A

No.A1954-3/31

Serial interfaces

• SIO0: 8-bit synchronous SIO

<1> LSB first/MSB first selectable

<2> Supports communication of less than 8 bits (1 to 8 bits specifiable).

<3> Built-in 8-bit baudrate generator (transfer clock cycles of 4 tCYC to 512 tCYC)

<4> Automatic continuous data transfer (9 to 32768 bits specifiable in 1-bit units)

<5> Interval function (interval time specifiable in 0 to 64 tSCK units)

<6> Wakeup function

• SMIIC0: Single-master I

Mode 0: Single-master master mode communication

Mode 1: 8-bit synchronous serial I/O (MSB first)

• UART0

<1> Data length: 8 bits (LSB first)

<2> Start bits: 1 bit

<3> Stop bits: 1 bit

<4> Parity bits: None/even parity/odd parity

<5> Transfer rate: 4/8 tCYC

<6> Baudrate clock source: The P07 input signal is used as a 1 cycle signal (T0PWMH can be used as the clock

source) or a timer 4 period.

<7> Full duplex communication

• UART2

<1> Data length: 8 bits (LSB first)

<2> Start bits: 1 bit

<3> Stop bits: 1/2 bit

<4> Parity bit: None/even parity/odd parity

<5> Transfer rate: 8 to 4096 tCYC

<6> Baudrate clock source: System clock/OSC0/OSC1/P21 input signal

<7> Wakeup function

<8> Full duplex communication

AD converter

<1> 8/12-bit resolution selectable

<2> Analog inputs: 12 channels

<3> Comparator mode

<4> Automatic reference voltage generation

Watchdog timer

<1> Runs on the base timer + internal watchdog timer dedicated counter.

<2> Interrupt or reset signals selectable

Infrared remote control receiver

<1> Noise rejection function

(Noise filter time constant: Approx. 120

μs when the 32.768kHz crystal oscillator is selected as the reference

clock source)

<2> Supports PPM (Pulse Position Modulation), Manchester and other encoding systems.

<3> HOLDX mode release function

Interrupts (peripheral function)

Either "Normal" or "LC888300 Compatible" mode is selectable by user option.

* Note: The "LC888300 Compatible" mode is an option that is available to provide compatibility between this model

and the LC888300. It is to be unavailable in future developed models.

<1> Provides three levels of multiplex interrupt control. Any interrupt request of the level equal to or lower than the

current interrupt is not accepted.

<2> When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level

takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector

address takes precedence.