No.

Control block/data

Function

Related data

No. 5815-11/23

LC72121, 72121M, 72121V

Continued from preceding page.

No.

Control block/data

Function

Related data

9

Clock time base

TBC

• Setting the TBC bit to 1 causes an 8-Hz clock time base signal with a 40% duty to be output from the

BO1 pin. (The BO1 data will be ignored.)

BO1

10

Charge pump

control data

DLC

• Forcibly controls the charge pump output.

* If the circuit deadlocks due to the VCO control voltage (Vtune) being 0 and the VCO being stopped,

applications can get out of the deadlocked state by setting the charge pump output to low and setting

11

IF counter control

data

IFS

• This data is normally set to 1. Setting this data to 0 sets the circuit to reduced input sensitivity mode, in

which the sensitivity is reduced by about 10 to 30 mV rms.

* See the “IF Counter Operation” section for details.

1

I/O port data

12, I1

• Data latched from the I/O port IO1 or IO2 pin states.

• These bits reflect the pin states regardless of the I/O port mode (input or output).

The data is latched at the point the circuit enters data output mode (OUT mode).

I1

← The IO1 pin state

H : 1

I2

← The IO2 pin state

L : 0

IOC1

IOC2

12

Test data

TEST0 to 2

• Test data

TEST0

TEST1

All these bits must be set to 0.

TEST2

All these bits are set to 0 after a power on reset.

13

DNC

• This bit must be set to 0.

DLC

Charge pump output

0

Normal operation

1

Forced to low

Structure of the DO Output Data (serial data output)

• OUT mode

DO Output Data

2

PLL unlocked state

data

UL

• Indicates the state of the unlocked state detection circuit.

UL

← 0: When the PLL is unlocked.

UL

← 1: When the PLL is locked or in the detection disabled mode.

UL0

UL1

3

IF counter binary

data

C19 to C0

• Indicates the value of the IF counter (20-bit binary counter).

C19

← MSB of the binary counter

C0

← LSB of the binary counter

CTE

GT0

GT1