AN811

Vishay Siliconix

Document Number: 71126

12-Dec-03

www.vishay.com

1

Single-Channel 1206-8 ChipFETr Power MOSFET Recommended

Pad Pattern and Thermal Performance

INTRODUCTION

New Vishay Siliconix ChipFETs in the leadless 1206-8

package feature the same outline as popular 1206-8 resistors

and capacitors but provide all the performance of true power

semiconductor devices. The 1206-8 ChipFET has the same

footprint as the body of the LITTLE FOOTR TSOP-6, and can

be thought of as a leadless TSOP-6 for purposes of visualizing

board area, but its thermal performance bears comparison

with the much larger SO-8.

This technical note discusses the single-channel ChipFET

1206-8 pin-out, package outline, pad patterns, evaluation

board layout, and thermal performance.

PIN-OUT

Figure 1 shows the pin-out description and Pin 1 identification

for the single-channel 1206-8 ChipFET device. The pin-out is

similar to the TSOP-6 configuration, with two additional drain

pins to enhance power dissipation and thermal performance.

The legs of the device are very short, again helping to reduce

the thermal path to the external heatsink/pcb and allowing a

larger die to be fitted in the device if necessary.

Single 1206-8 ChipFET

D

D

D

G

D

D

D

S

1

Bottom View

FIGURE 1.

For package dimensions see the 1206-8 ChipFET package

BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in Application

Note 826, Recommended Minimum Pad Patterns With Outline

Drawing

Access

for

Vishay Siliconix

MOSFETs,

power dissipation MOSFET applications, but power

semiconductor performance requires a greater copper pad

area, particularly for the drain leads.

FIGURE 2. Footprint With Copper Spreading

80 mil

68 mil

28 mil

26 mil

The pad pattern with copper spreading shown in Figure 2

improves the thermal area of the drain connections (pins

1,2,3,6.7,8) while remaining within the confines of the basic

footprint. The drain copper area is 0.0054 sq. in. or

3.51 sq. mm). This will assist the power dissipation path away

from the device (through the copper leadframe) and into the

board and exterior chassis (if applicable) for the single device.

The addition of a further copper area and/or the addition of vias

to other board layers will enhance the performance still further.

An example of this method is implemented on the

Vishay Siliconix Evaluation Board described in the next

section (Figure 3).

THE VISHAY SILICONIX EVALUATION

BOARD FOR THE SINGLE 1206-8

The ChipFET 1206-08 evaluation board measures 0.6 in by

0.5 in. Its copper pad pattern consists of an increased pad area

around the six drain leads on the top-side—approximately

0.0482 sq. in. 31.1 sq. mm—and vias added through to the

underside of the board, again with a maximized copper pad

area of approximately the board-size dimensions. The outer

package outline is for the 8-pin DIP, which will allow test

sockets to be used to assist in testing.

The thermal performance of the 1206-8 on this board has been

measured with the results following on the next page. The

testing included comparison with the minimum recommended

footprint on the evaluation board-size pcb and the industry

standard one-inch square FR4 pcb with copper on both sides

of the board.