ADP1853 datasheet(4/28 Pages) AD

Numer części	ADP1853

Szczegółowy opis	Synchronous, Step-Down DC-to-DC Controller

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Producent	AD [Analog Devices]

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ADP1853

Data Sheet

Rev. 0 | Page 4 of 28

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

LOGIC INPUTS

EN

EN rising

0.57

0.63

0.68

V

EN Hysteresis

0.03

V

EN Input Leakage Current

I

EN

V

IN = 2.75 V to 20 V

1

200

nA

SYNC Logic Input Low

1.3

V

SYNC Logic Input High

1.9

V

SYNC Input Pull-Down Resistance

R

SYNC

1

MΩ

GATE DRIVERS

DH Rise Time

C

DH = 3 nF, VBST − VSW = 5 V

16

ns

DH Fall Time

C

DH = 3 nF, VBST − VSW = 5 V

14

ns

DL Rise Time

C

DL = 3 nF

16

ns

DL Fall Time

C

DL = 3 nF

14

ns

DH to DL Dead Time

External 3 nF is connected to DH and DL

25

ns

DH or DL Driver R

ON, Sourcing

Current1

R

ON_SOURCE

Sourcing 2 A with a 100 ns pulse

2

Ω

Sourcing 1 A with a 100 ns pulse, V

IN = 3 V

2.3

Ω

DH or DL Driver R

ON, Tempco

TC

RON

V

IN = 3 V or 12 V

0.3

%/oC

DH or DL Driver R

ON, Sinking

Current1

R

ON_SINK

Sinking 2 A with a 100 ns pulse

1.5

Ω

Sinking 1 A with a 100 ns pulse, V

IN = 3 V

2

Ω

DH Maximum Duty Cycle1

f

OSC = 300 kHz

90

%

DH Maximum Duty Cycle1

f

OSC = 1500 kHz

50

%

Minimum DH On Time

f

OSC = 200 kHz to 1500 kHz

85

ns

Minimum DH Off Time

f

OSC = 200 kHz to 1500 kHz

345

ns

Minimum DL On Time

f

OSC = 200 kHz to 1500 kHz

295

ns

COMP VOLTAGE RANGE

COMP Pulse Skip Threshold

V

COMP,THRES

In pulse skip mode (PSM)

0.9

V

COMP Clamp High Voltage

V

COMP,HIGH

2.2

V

THERMAL SHUTDOWN

Thermal Shutdown Threshold

T

TMSD

155

°C

Thermal Shutdown Hysteresis

20

°C

OVERVOLTAGE AND POWER GOOD

THRESHOLDS

FB Overvoltage Threshold

V

OV

V

FB rising

0.630

0.65

0.670

V

FB Overvoltage Hysteresis

18

mV

FB Undervoltage Threshold

V

UV

V

FB falling

0.525

0.55

0.575

V

FB Undervoltage Hysteresis

15

mV

TRK INPUT VOLTAGE RANGE1

0

5

V

FB TO TRK OFFSET VOLTAGE

TRK = 0.1 V to 0.57 V; offset = V

FB − VTRK

−10

0

+10

mV

SOFT START

SS Output Current

I

SS

During startup

4.6

6.5

8.4

µA

SS Pull-Down Resistor

During a fault condition

3

kΩ

FB to SS offset

V

SS = 0.1 V to 0.6 V; offset = VFB − VSS

−10

+10

mV

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