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CBC3225T1R0MR Arkusz danych(PDF) 1 Page - Analog Devices

Numer części CBC3225T1R0MR
Szczegółowy opis  Dual 3 MHz, 1200 mA Buck
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Strona internetowa  http://www.analog.com
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Dual 3 MHz, 1200 mA Buck
Regulators with One 300 mA LDO
Data Sheet
ADP5024
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011-2012 Analog Devices, Inc. All rights reserved.
FEATURES
Main input voltage range: 2.3 V to 5.5 V
Two 1200 mA buck regulators and one 300 mA LDO
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±3%
Factory programmable or external adjustable VOUTx
3 MHz buck operation with forced PWM and automatic
PWM/PSM modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
LDO: output voltage range from 0.8 V to 5.2 V
LDO: input supply voltage from 1.7 V to 5.5 V
LDO: high PSRR and low output noise
APPLICATIONS
Power for processors, ASICS, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices
GENERAL DESCRIPTION
The ADP5024 combines two high performance buck regula-
tors and one low dropout (LDO) regulator in a small, 24-lead,
4 mm × 4 mm LFCSP to meet demanding performance and
board space requirements.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set high, the buck regulators operate in
forced PWM mode. When the MODE pin is set low, the buck
regulators operate in PWM mode when the load current is above
a predefined threshold. When the load current falls below a pre-
defined threshold, the regulator operates in power save mode
(PSM), improving the light load efficiency.
The two bucks operate out of phase to reduce the input capacitor
requirement. The low quiescent current, low dropout voltage, and
wide input voltage range of the LDO extends the battery life of
portable devices. The ADP5024 LDO maintains power supply
rejection greater than 60 dB for frequencies as high as 10 kHz
while operating with a low headroom voltage.
Regulators in the ADP5024 are activated though dedicated
enable pins. The default output voltages can be either externally
set in the adjustable version or factory programmable to a wide
range of preset values in the fixed voltage version.
TYPICAL APPLICATION CIRCUIT
VIN1
VIN3
EN1
PWM
PSM/PWM
2.3V TO
5.5V
SW1
FB1
R2
R1
VOUT1
PGND1
MODE
C5
10µF
VOUT1 AT
1200mA
VOUT2 AT
1200mA
VOUT3 AT
300mA
L1 1µH
EN1
BUCK1
MODE
C3
1µF
C2
4.7µF
C1
4.7µF
AVIN
CAVIN
0.1µF
VIN2
EN2
AGND
EN2
BUCK2
MODE
EN3
1.7V TO
5.5V
ON
OFF
ON
OFF
EN3
LDO
(ANALOG)
HOUSEKEEPING
SW2
FB2
R4
R3
VOUT2
PGND2
C6
10µF
L2 1µH
FB3
R6
R5
VOUT3
C7
1µF
ADP5024
Figure 1.


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