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ADUM1280CRZ-RL7 Arkusz danych(PDF) 5 Page - Analog Devices

Numer części ADUM1280CRZ-RL7
Szczegółowy opis  3 kV RMS Dual Channel Digital Isolators
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ADUM1280CRZ-RL7 Arkusz danych(HTML) 5 Page - Analog Devices

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Data Sheet
ADuM1280/ADuM1281/ADuM1285/ADuM1286
Rev. 0 | Page 5 of 16
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 5 V, VDD2 = 3.0 V. Minimum/maximum specifications apply over the entire
recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; and −40°C ≤ TA ≤ 125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels unless otherwise noted.
Table 7.
A Grade
B Grade
C Grade
Parameter
Symbol
Min
Typ
Min
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions
SWITCHING SPECIFICATIONS
Pulse Width
PW
1000
40
10
ns
Within PWD limit
Data Rate
1
25
100
Mbps
Within PWD limit
Propagation Delay
tPHL, tPLH
50
35
13
20
26
ns
50% input to 50% output
Pulse Width Distortion
PWD
10
3
2
ns
|tPLH − tPHL|
Change vs. Temperature
7
3
1.5
ps/C
Propagation Delay Skew
tPSK
38
16
12
ns
Between any two units
at same operating
conditions
Channel Matching
Codirectional
tPSKCD
5
3
2
ns
Opposing-Direction
tPSKOD
10
6
5
ns
Jitter
2
2
1
ns
7 Codirectional channel matching is the absolute value of the difference in propagation delays between any two c hannels with inputs on the same side of the isolation barrier. Opposing-directional channel matching is the absolute value of the difference in propagation delays between any two c hannels wit h inputs on opposing sides of the isolation barrier.
Table 8.
Parameter
Symbol
1 Mbps–A, B, C Grade
25 Mbps–B, C Grade
100 Mbps–C Grade
Unit
Test Conditions
Min
Typ
Min
Min
Typ
Max
Min
Typ
Max
SUPPLY CURRENT
No load
ADuM1280/ADuM1285
IDD1
1.1
1.6
6.2
7.0
20
25
mA
IDD2
2.0
3.5
2.7
4.6
4.8
9.0
mA
ADuM1281/ADuM1286
IDD1
2.1
2.6
4.9
6.0
15
19
mA
IDD2
1.7
2.3
3.9
6.2
11
15
mA
Table 9. For All Models
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Logic High Input Threshold
VIH
0.7 VDDx
V
Logic Low Input Threshold
VIL
0.3 VDDx
V
Logic High Output Voltages
VOH
VDDx − 0.1
VDDx
V
IOx = −20 µA, VIx = VIxH
VDDx−0.4
VDDx−0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOL
0.0
0.1
V
IOx = 20 µA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
Input Current per Channel
II
−10
+0.01
+10
µA
0 V ≤ VIx≤ VDDx
Supply Current per Channel
Quiescent Input Supply Current
IDDI(Q)
0.54
0.75
mA
Quiescent Output Supply Current
IDDO(Q)
1.2
2.0
mA
Dynamic Input Supply Current
IDDI(D)
0.09
mA/Mbps
Dynamic Output Supply Current
IDDO(D)
0.02
mA/Mbps
Undervoltage Lockout
Positive VDDX Threshold
VDDxUV+
2.6
V
Negative VDDX Threshold
VDDxUV−
2.4
V
VDDX Hysteresis
VDDxUVH
0.2
V
AC SPECIFICATIONS
Output Rise/Fall Time
tR/tF
2.5
ns
10% to 90%
Common-Mode Transient Immunity1
|CM|
25
35
kV/µs
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
Refresh Period
tr
1.6
µs
1|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining V
o > 0.8 VDDX. The common-mode voltage slew rates apply to both
rising and falling common-mode voltage edges.


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