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ADXL362 Arkusz danych(PDF) 13 Page - Analog Devices |
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ADXL362 Arkusz danych(HTML) 13 Page - Analog Devices |
13 / 40 page Preliminary Technical Data ADXL362 Rev. PrB | Page 13 of 40 ADDITIONAL FEATURES FREE-FALL DETECTION Many digital-output accelerometers include a built-in free-fall detection feature. In the ADXL362, this function can be implemented using the Inactivity interrupt. Refer to the Applications Information section on page 31 for more details including suggested threshold and timing values. SELECTABLE OUTPUT DATA RATES The ADXL362 can report acceleration data at various data rates ranging from 12.5 Hz to 400 Hz. The internal low-pass filter pole is automatically set to ¼ or ½ the selected ODR, based on the HALF_BW to ensure the Nyquist sampling criterion is met and no aliasing occurs. Current consumption varies somewhat with output data rate as shown in Figure 4, remaining below 5.0 µA over the entire range of data rates and operating voltages. Figure 4. Current Consumption vs Output Data Rate at Several Supply Voltages SELECTABLE MEASUREMENT RANGES The ADXL362 has a selectable measurement ranges of ±2, ±4, and ±8 g. Acceleration samples are always converted by a 12-bit analog-to-digital converter (ADC), so sensitivity scales with g- range. Ranges and corresponding sensitivity values are listed in Table 1. When acceleration exceeds the measurement extremes, data is clipped at the measurement range value, but no damage is caused to the accelerometer. The Absolute Maximum Ratings for acceleration on Page 3 indicates the acceleration level at which permanent damage may be caused to the device. USING AN EXTERNAL CLOCK The ADXL362 has a built-in clock that, by default, serves as the time base for internal operations. If desired, an external clock may be provided instead. The external clock must operate at 51.2 kHz ± TBD%. ODR and bandwidth scale proportionally with the clock. The ADXL362 provides a discrete number of options for ODR. Output data rates other than those provided can be achieved by selecting an appropriate clock frequency. For example, to achieve an 80 Hz ODR, the 100 Hz setting can be used with a clock frequency that is 80% of nominal, or 41.0 kHz. Bandwidth automatically scales to ½ or ¼ of the ODR (based on the HALF_BW setting), and this ratio is preserved regardless of clock frequency. Power consumption also scales with clock frequency: higher clock rates increase power consumption. Figure 5 shows how power consumption varies with clock rate. Figure 5. Current Consumption vs External Clock Rate [PLACEHOLDER] SYNCHRONIZED DATA SAMPLING For applications that require a precisely timed acceleration measurement, the ADXL362 features an option to synchronize acceleration sampling to an external trigger. SELF TEST The ADXL362 incorporates a self-test feature that effectively tests its mechanical and electronic systems simultaneously. When the self-test function is invoked, an electrostatic force is applied to the mechanical sensor. This electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is additive to the acceleration experienced by the device. This added electrostatic force results in an output change in all three axes. USER REGISTER PROTECTION The ADXL362 includes user register protection for single event upsets (SEUs). A single event upset (SEU) is a change of state caused by ions or electromagnetic radiation striking a sensitive node in a microelectronic device. The state change is a result of the free charge created by ionization in or close to an important node of a logic element (for example, memory "bit"). The SEU itself is not considered permanently damaging to transistor or circuit functionality, but can create erroneous register values. |
Podobny numer części - ADXL362 |
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Podobny opis - ADXL362 |
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