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ES51997 Arkusz danych(PDF) 7 Page - Cyrustek corporation |
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ES51997 Arkusz danych(HTML) 7 Page - Cyrustek corporation |
7 / 28 page ver. 1.7 12/01/12 7 ES51997(60000counts) DMM Analog front end AC electrical characteristics Parameter Symbol Min. Typ. Max. Unit SCLK clock frequency fSCLK - - 100 kHz SCLK clock time “L” tLOW 4.7 - - us SLCK clock time “H” tHIGH 4.0 - - SDATA output delay time tAA 0.1 - 3.5 SDATA output hold time tDH 100 - - ns Start condition setup time tSU.STA 4.7 - - us Start condition hold time tHD.STA 4.0 - - Data input setup time tSU.DAT 200 - - ns Data input hold time tHD.DAT 0 - - Stop condition setup time tSU.STO 4.7 - - us SCLK/SDATA rising time tR - - 1.0 SCLK/SDATA falling time tF - - 0.3 Bus release time tBUF 4.7 - - EOC setup time in read mode tSU.EOC 0 ns EOC hold time in read mode tHD.EOC 0 - - ns MPU I/O timing diagram SCLK SDATA IN SDATA OUT |
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