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SLA24C32-S Arkusz danych(PDF) 11 Page - Siemens Semiconductor Group |
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SLA24C32-S Arkusz danych(HTML) 11 Page - Siemens Semiconductor Group |
11 / 26 page SLx 24C32 Semiconductor Group 11 Preliminary 1998-07-27 5 Write Operations Changing of the EEPROM data is initiated by the master with the command byte CSW. Either one byte (Byte Write) or up to 32 byte (Page Write) are modified in one programming procedure. Setting the Write Protection pin WP to V CC activates the hardware write protection and therefore any programming is suppressed. For normal operation WP has to be set to V SS. 5.1 Byte Write Figure 7 Byte Write Sequence The erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for speed enhancement in order to detect the end of the erase/write cycle. Please refer to chapter 5.3, Acknowledge Polling for further information. Address Setting After a START condition the master transmits the Chip Select Write byte CSW. The EEPROM acknowledges the CSW byte during the ninth clock cycle. The following two bytes AHI/ALO with the EEPROM address (A0 to A11) are loaded into the address counter of the EEPROM and acknowledged by the EEPROM. Transmission of Data Finally the master transmits the data byte which is also acknowledged by the EEPROM into the internal buffer. Programming Cycle Then the master applies a STOP condition which starts the internal programming procedure. The data bytes are written in the memory location addressed in the bytes AHI (A8 to A11) and ALO (A0 to A7). The programming procedure consists of an internally timed erase/write cycle. In the first step, the selected byte is erased to “1”. With the next internal step, the addressed byte is written according to the contents of the buffer. Command Byte CSW S P C K A C K A S T A R T T P O S EEPROM Address AHI Data Byte Bus Activity Master SDA Line Bus Activity EEPROM IED02518 C K A 0 EEPROM Address ALO C K A |
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