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CDCM9102RHBT Arkusz danych(PDF) 11 Page - Texas Instruments |
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CDCM9102RHBT Arkusz danych(HTML) 11 Page - Texas Instruments |
11 / 22 page REF REF 1 t = = 0.04 s f CDCM9102 www.ti.com SCAS922 – FEBRUARY 2012 C0 = 7 pF (shunt capacitance) CS = 10 fF (motional capacitance) CLr = 12 pF (load capacitance) Substituting these parameters into Equation 1 yields a maximum value of CLa = 17 pF in order to achieve the desired Δf (±50 ppm). Recall that CLa = CIN + CL + CSTRAY + CPARASITIC = 8 pF + (CL + CSTRAY + CPARASITIC) (1) . Ideally, the load presented to this crystal should be 12 pF; therefore the sum of (CL + CSTRAY + CPARASITIC) must be less than 9 pF. Stray and parasitic capacitance must be controlled. This is because the Colpitts oscillator is particularly sensitive to capacitance in parallel with the crystal; therefore, good layout practice is essential. It is recommended that the designer extract the stray and parasitic capacitance from the printed circuit board design tool and adjust CL accordingly to achieve CLr = CLa. In common scenarios, the external load capacitor is often unnecessary; however, it is recommended that pads be implemented to accommodate an external load capacitor so that the ppm error can be minimized. STARTUP TIME ESTIMATION The CDCM9102 contains a low-noise clock generator that calibrates to an optimal operating point at device power up. In order to ensure proper device operation, the oscillator must be stable prior to the low-noise clock generator calibration procedure. Quartz-based oscillators can take up to 2 ms to stabilize; therefore it is recommended that the application ensure that the RESET pin is de-asserted at least 5 ms after the power supply has finished ramping. This can be accomplished by controlling the RESET pin directly, or by applying a 47-nF capacitor to ground on the RESET pin (this provides a delay because the RESET pin includes a 150-k Ω pullup resistor. The CDCM9102 startup time can be estimated based on parameters defined in Table 5 and graphically shown in Figure 12. Table 5. CDCM9102 Startup Time Dependencies Parameter Definition Description Formula / Method of Determination The reciprocal of the applied reference tREF Reference clock period frequency in seconds Power-supply rise time to low limit of tpul Power-up time (low limit) Time required for power supply to ramp to 2.27 V power-on-reset trip point Power supply rise time to high limit of tpuh Power-up time (high limit) Time required for power supply to ramp to 2.64 V power-on-reset trip point After POR releases, the Colpitts oscillator is enabled. This start-up time is required for the 500 μs best case and 800 μs worst case (for a crystal trsu Reference start-up time oscillator to generate the requisite signal input) levels for the delay block to be clocked by the reference input. Internal delay time generated from the tdelay Delay time reference clock. This delay provides time for tdelay = 16,384 × tREF = 655 µs the reference oscillator to stabilize. VCO calibration time generated from the reference clock. This process selects the tVCO_CAL VCO calibration time tVCO_CAL = 550 × tREF = 22 µs operating point for the VCO based on the PLL settings. Time requried for PLL to lock within ±10 ppm tPLL_LOCK PLL lock time The PLL settles in 12.5 μs of fREF (1) CIN = 8 pF (typical), 10 pF (maximum). See the Crystal Oscillator Input Port Characteristics (XIN) table. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): CDCM9102 |
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