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CDCM9102RHBR Arkusz danych(PDF) 10 Page - Texas Instruments

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Numer części CDCM9102RHBR
Szczegółowy opis  Low-Noise Two-Channel 100-MHz Clock Generator
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CDCM9102RHBR Arkusz danych(HTML) 10 Page - Texas Instruments

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XO
25 MHz
C
STRAY
C
PARASITIC
C
L
C
IN
XIN
(Pin 21)
(
) (
)
C
C
S
S
=
-
2 C
+ C
2 C
+ C
Lr
La
O
O
f
f
CDCM9102
SCAS922
– FEBRUARY 2012
www.ti.com
APPLICATION INFORMATION
CRYSTAL INPUT (XIN) INTERFACE
The CDCM9102 implements a Colpitts oscillator; therefore, one side of the crystal connects to the XIN pin and
the other crystal terminal connects to ground. The device requires the use of a fundamental-mode crystal, and
the oscillator operates in parallel resonance mode. The correct load capacitance is necessary to ensure that the
circuit oscillates properly. The load capacitance comprises all capacitances in the oscillator feedback loop (the
capacitances seen between the terminals of the crystal in the circuit). It is important to account for all sources of
capacitance when calculating the correct value for the external discrete load capacitance shown in Figure 11.
Figure 11. Configuration of Circuit for CDCM9102 XIN Oscillator
The CDCM9102 has been characterized with 10-pF parallel-resonant crystals. The input stage of the crystal
oscillator in the CDCM9102 is designed to oscillate at the correct frequency for all parallel-resonant crystals with
low-pull capability and rated with a load capacitance that is equal to the sum of the on-chip load capacitance at
the XIN pin (CIN = 10 pF maximum), crystal stray capacitance, and board parasitic capacitance between the
crystal and XIN pin. To minimize stray and parasitic capacitances, minimize the trace distance routed from the
crystal to the XIN pin and avoid other active traces and/or active circuitry in the area of the crystal oscillator
circuit. Table 4 lists crystal types that have been evaluated with the CDCM9102.
Table 4. CDCM9102 Crystal Recommendations
MANUFACTURER
PART NUMBER
Vectron
VXC1-1133
Fox
218-3
Saronix
FP2650002
A mismatch of the load capacitance results in a frequency error according to Equation 1:
(1)
where:
Δƒ is the frequency error required by the application.
f is the fundamental frequency of the crystal.
CS is the motional capacitance of the crystal. This is a parameter in the data sheet of the crystal.
C0 is the shunt capacitance of the crystal. This is a parameter in the data sheet of the crystal.
CLr is the rated load capacitance of the crystal. This is a parameter in the data sheet of the crystal.
CLa is the actual load capacitance implemented on the PCB (CIN + stray capacitance + parasitic capacitance
+ CL).
The difference between the rated load capacitance (from the crystal datasheet) and the actual load capacitance
(CLa = CIN + CL + CSTRAY + CPARASITIC) should be minimized. A crystal with a low pull-ability rating (low CS) is
ideal.
Design Example:
Desired frequency tolerance
Δf ≤ ±80 ppm
Crystal Vendor Parameters:
Intrinsic Frequency Tolerance =
±30 ppm
10
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Copyright
© 2012, Texas Instruments Incorporated
Product Folder Link(s): CDCM9102


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