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SL74HC109 Arkusz danych(PDF) 4 Page - System Logic Semiconductor |
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SL74HC109 Arkusz danych(HTML) 4 Page - System Logic Semiconductor |
4 / 5 page SL74HC109 System Logic Semiconductor SLS AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 4.5 6.0 6 30 35 4.8 24 28 4.0 20 24 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tPLH, tPHL Maximum Propagation Delay , Set or Reset to Q or Q (Figures 2 and 4) 2.0 4.5 6.0 230 46 39 290 58 49 345 69 59 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns CIN Maximum Input Capacitance - 10 10 10 pF Power Dissipation Capacitance (Per Flip-Flop) Typical @25°C,VCC=5.0 V CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC 2 f+ICCVCC 40 pF TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit tSU Minimum Setup Time, J or K to Clock (Figure 3) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns th Minimum Hold Time, Clock to J or K (Figure 3) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns trec Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns tw Minimum Pulse Width, Set or Reset (Figure 2) 2.0 4.5 6.0 80 16 14 100 20 17 12 24 20 ns tw Minimum Pulse Width,Clock (Figure 1) 2.0 4.5 6.0 80 16 14 100 20 17 12 24 20 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns |
Podobny numer części - SL74HC109 |
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Podobny opis - SL74HC109 |
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