74ACT11478

METASTABLERESISTAND OCTAL DTYPE DUALRANK FLIPFLOP

WITH 3-STATE OUTPUTS

SCAS131 − APRIL 1990 − REVISED APRIL 1993

4

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance per flip-flop

Outputs enabled

CL = 50 pF,

f = 1 MHz

76

pF

Cpd

Power dissipation capacitance per flip-flop

Outputs disabled

CL = 50 pF,

f = 1 MHz

64

pF

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

2 X VCC

Open

GND

500

Ω

500

Ω

TEST

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

S1

Open

2 x VCC

GND

1.5 V

1.5 V

1.5 V

3 V

3 V

0 V

0 V

th

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Data

Input

3 V

0

3 V

0

1.5 V

1.5 V

1.5 V

1.5 V

tw

High-Level

Input

Low-Level

Input

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

1.5 V

1.5 V

3 V

0

50%

50%

Input

(see Note B)

Out-of-Phase

Output

In-Phase

Output

Output

Control

(Low-Level

Enabling)

Output

Waveform 1

S1 at 2 x VCC

(see Note C)

Output

Waveform 2

S1 at GND

(see Note C)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

0

50%

20%

50%

80%

ENABLE AND DISABLE TIMES

VOLTAGE WAVEFORMS

3 V

Timing Input

(see Note B)

50%

50%

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms