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ADS1000-Q1 Arkusz danych(PDF) 6 Page - Texas Instruments

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Numer części ADS1000-Q1
Szczegółowy opis  LOW-POWER 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH I2C??INTERFACE
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ADS1000-Q1
SBAS480A – SEPTEMBER 2009 – REVISED AUGUST 2010
www.ti.com
I2C INTERFACE
The ADS1000 communicates through an I2C (Inter-Integrated Circuit) interface. The I2C interface is a two-wire,
open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive
the bus lines low, by connecting them to ground; they never drive the bus lines high. Instead, the bus wires are
pulled high by pullup resistors, so the bus wires are high when no device is driving them low. This way, two
devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.
Communication on the I2C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of
the master. Some I2C devices can act as masters or slaves, but the ADS1000 can only act as a slave device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted
across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the bit level
while SCL is low (a Low on SDA indicates the bit is 0; a High indicates the bit is 1). Once the SDA line has
settled, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the receiver shift
register.
The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads
from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. The
master always drives the clock line. The ADS1000 never drives SCL, because it cannot act as a master. On the
ADS1000, SCL is an input only.
Most of the time the bus is idle, no communication takes place, and both lines are high. When communication
takes place, the bus is active. Only master devices can start a communication. They do this by causing a start
condition on the bus. Normally, the data line is only allowed to change state while the clock line is low. If the data
line changes state while the clock line is high, it is either a start condition or its counterpart, a stop condition. A
start condition is when the clock line is high and the data line goes from high to low. A stop condition is when the
clock line is high and the data line goes from low to high.
After the master issues a start condition, it sends a byte that indicates with which slave device it wants to
communicate. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to
which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master
sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to
the slave device.
Every byte transmitted on the I2C bus, whether it be address or data, is acknowledged with an acknowledge bit.
When a master has finished sending a byte, eight data bits, to a slave, it stops driving SDA and waits for the
slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a
clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA low
to acknowledge to the slave that it has finished reading the byte. It then sends a clock pulse to clock the bit.
(Remember that the master always drives the clock line.)
A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. If a device is not
present on the bus, and the master attempts to address it, it will receive a not-acknowledge because no device is
present at that address to pull the line low.
When a master has finished communicating with a slave, it may issue a stop condition. When a stop condition is
issued, the bus becomes idle again. A master may also issue another start condition. When a start condition is
issued while the bus is active, it is called a repeated start condition.
A timing diagram for an ADS1000 I2C transaction is shown in Figure 6. Table 1 gives the parameters for this
diagram.
6
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