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ADS1282HPW Arkusz danych(PDF) 6 Page - Texas Instruments |
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ADS1282HPW Arkusz danych(HTML) 6 Page - Texas Instruments |
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6 / 60 page  ADS1282-HT SBAS446F – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). ADS1282 UNIT AVDD to AVSS –0.3 to 5.5 V AVSS to DGND –2.8 to 0.3 V DVDD to DGND –0.3 to 3.9 V Input current 100, momentary mA Input current 10, continuous mA Analog input voltage AVSS – 0.3 to AVDD + 0.3 V Digital input voltage to DGND –0.3 to DVDD + 0.3 V KGD and JDJ packages –55 to 210 Operating temperature range °C PW package –55 to 175 Storage temperature range –60 to 210 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. THERMAL INFORMATION ADS1282 THERMAL METRIC JDJ PW UNITS 28 PINS 28 PINS θJA Junction-to-ambient thermal resistance(1) 43.1 54.6 θJCtop Junction-to-case (top) thermal resistance(2) 14.03 11.3 θJB Junction-to-board thermal resistance(3) 23.2 13 °C/W ψJT Junction-to-top characterization parameter(4) n/a 0.5 ψJB Junction-to-board characterization parameter(5) n/a 12.7 θJCbot Junction-to-case (bottom) thermal resistance(6) 4.98 n/a (1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6 Copyright © 2009–2011, Texas Instruments Incorporated |
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