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ADS5292IPFP Arkusz danych(PDF) 4 Page - Texas Instruments |
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ADS5292IPFP Arkusz danych(HTML) 4 Page - Texas Instruments |
4 / 67 page ADS5292 SLAS788B – NOVEMBER 2011 – REVISED JULY 2012 www.ti.com PIN FUNCTIONS (continued) PIN NUMBER DESCRIPTION OF PINS NAME NUMBER 2 OUT1B_P, OUT1B_N 15, 16 Differential LVDS data output, wire 2, channel 1 2 OUT2A_P, OUT2A_N 17, 18 Differential LVDS data output, wire 1, channel 2 2 OUT2B_P, OUT2B_N 19, 20 Differential LVDS data output, wire 2, channel 2 2 OUT3A_P, OUT3A_N 21, 22 Differential LVDS data output, wire 1, channel 3 2 OUT3B_P, OUT3B_N 23, 24 Differential LVDS data output, wire 2, channel 3 2 OUT4A_P, OUT4A_N 25, 26 Differential LVDS data output, wire 1, channel 4 2 OUT4B_P, OUT4B_N 27, 28 Differential LVDS data output, wire 2, channel 4 2 OUT5A_P, OUT5A_N 35, 36 Differential LVDS data output, wire 1, channel 5 2 OUT5B_P, OUT5B_N 33, 34 Differential LVDS data output, wire 2, channel 5 2 OUT6A_P, OUT6A_N 39, 40 Differential LVDS data output, wire 1, channel 6 2 OUT6B_P, OUT6B_N 37, 38 Differential LVDS data output, wire 2, channel 6 2 OUT7A_P, OUT7A_N 43, 44 Differential LVDS data output, wire 1, channel 7 2 OUT7B_P, OUT7B_N 41, 42 Differential LVDS data output, wire 2, channel 7 2 OUT8A_P, OUT8A_N 47, 48 Differential LVDS data output, wire 1, channel 8 2 OUT8B_P, OUT8B_N 45, 46 Differential LVDS data output, wire 2, channel 8 1 PD 10 Power down control input. Active High. The pin has an internal 220-k Ω pulldown resistor. 1 REFB 69 Negative reference input/ output 1 REFT 70 Positive reference input/ output 1 VCM 68 Common-mode output pin, 0.95 V output. This pin can be configured as the external reference voltage (1.5 V) input pin as well. See Reg 0x42. 1 RESET 51 Active HIGH RESET input. The pin has an internal 220-k Ω pulldown resistor. 1 SCLK 77 Serial clock input. The pin has an internal 220-k Ω pulldown resistor. 1 SDATA 76 Serial data input. The pin has an internal 220-k Ω pulldown resistor. 1 SDOUT 64 Serial data readout. This pin is in the high-impedance state after reset. When the <READOUT> bit is set, the SDOUT pin becomes active. This is a CMOS digital output running from the AVDD supply. 1 CSZ 75 Serial enable chip select – active low digital input 1 SYNC 65 Input signal to synchronize channels and chips when used with reduced output data rates. If it is not used, add a ≤ 10 KΩ pull-down resistor. 1 NC 67 No Connection. Must leave floated 4 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :ADS5292 |
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