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CD74HC20QM96Q1 Arkusz danych(PDF) 2 Page - Texas Instruments |
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CD74HC20QM96Q1 Arkusz danych(HTML) 2 Page - Texas Instruments |
2 / 7 page CD74HC20-Q1 HIGH-SPEED CMOS LOGIC DUAL 4-INPUT NAND GATE SCLS522 – AUGUST 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) nA nB nY nC nD absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC –0.5 V to 7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current, IIK (VI < –0.5 V or VI > VCC + 0.5 V) ±20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current, IOK (VO < –0.5 V or VO > VCC + 0.5 V) ±20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch current per output pin, IO (VO > –0.5 V or VO < VCC + 0.5 V) ±25 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous current through VCC or GND ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2) 86 °C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum junction temperature, TJ 150 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature (during soldering): At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max 300 °C . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65 °C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are referenced to GND, unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 2 6 V V High-level input voltage VCC = 2 V 1.5 V VIH High-level input voltage VCC = 4.5 V 3.15 V IH VCC = 6 V 4.2 V Low-level input voltage VCC = 2 V 0.5 V VIL Low-level input voltage VCC = 4.5 V 1.35 V IL VCC = 6 V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V t Input transition (rise and fall) time VCC = 2 V 0 1000 ns tt Input transition (rise and fall) time VCC = 4.5 V 0 500 ns t VCC = 6 V 0 400 TA Operating free-air temperature –40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. |
Podobny numer części - CD74HC20QM96Q1 |
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Podobny opis - CD74HC20QM96Q1 |
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