1

FEATURES

DESCRIPTION

SN74SSTUB32864

SCAS791A – OCTOBER 2006 – REVISED SEPTEMBER 2007

www.ti.com

25-BIT CONFIGURABLE REGISTERED BUFFER

• Supports SSTL_18 Data Inputs

2

• Member of the Texas Instruments Widebus+™

• Differential Clock (CLK and CLK) Inputs

Family

• Supports LVCMOS Switching Levels on the

• Pinout Optimizes DDR2 DIMM PCB Layout

Control and RESET Inputs

• Configurable as 25-Bit 1:1 or 14-Bit 1:2

• Supports Industrial Temperature Range

Registered Buffer

(-40

°C to 85°C)

• Chip-Select Inputs Gate the Data Outputs from

• RESET Input Disables Differential Input

Changing State and Minimizes System Power

Receivers, Resets All Registers, and Forces

Consumption

All Outputs Low

• Output Edge-Control Circuitry Minimizes

Switching Noise in an Unterminated Line

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the

1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout

configuration, two devices per DIMM are required to drive 18 SDRAM loads.

All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are

edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.

The SN74SSTUB32864 operates from a differential clock (CLK and CLK). Data are registered at the crossing of

CLK going high and CLK going low.

The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to

register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to

14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to

a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the

A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and

CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is

cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input

receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required

to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the

time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the

SN74SSTUB32864 ensures that the outputs remain low, thus ensuring there will be no glitches on the output.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the

low state during power up.

The device supports low-power standby operation. When RESET is low, the differential input receivers are

RESET is low, all registers are reset and all outputs are forced low, except QERR. The LVCMOS RESET and Cn

inputs always must be held at a valid logic high or low level.

ORDERING INFORMATION

ORDERABLE PART NUMBER

TOP-SIDE MARKING

-40

°C to 85°C

LFBGA–ZKE

Tape and reel

SN74SSTUB32864ZKER

SB864

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

Widebus+ is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 2006–2007, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.