TL5632 datasheet(6/10 Pages) TI1

Numer części	TL5632

Szczegółowy opis	8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER

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Producent	TI1 [Texas Instruments]

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TL5632C

8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER

SLAS091 – DECEMBER 1994

6

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

The following design procedures should be used for optimum operation.

D External analog and digital circuitry should be physically separated and shielded as much as possible to

reduce system noise.

D RF breadboarding or RF printed-circuit-board (PCB) techniques should be used throughout the evaluation

and production process.

D Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance

and resistance. A ground plane is the better choice for noise reduction.

D AVCC and DVCC are also separate internally, so they must be connected externally. These external PCB

leads should also be made as wide as possible. A ferrite bead or equivalent inductance should be placed

in series with AVCC and the decoupling capacitor before the AVCC and DVCC leads are connected together

on the board. It is critical that the supply voltage applied to AVCC be as noise free and ripple free as possible.

Ripple and noise rejection should be a minimum of 60 dB below the full-scale output range of 1 V

peak-to-peak.

D AVCC to GND and DVCC to GND should be decoupled with 3.3-µF and 0.1-µF capacitors, respectively, as

close as possible to the appropriate device terminals. A ceramic chip capacitor is recommended for the

0.1-

µF capacitor.

D The phase compensation capacitor should be connected between CCOMP and GND with as short a lead-in

as possible.

D The no-connection (NC) terminals on the small-outline package should be connected to GND.

D AVCC, DVCC, and ROUT, GOUT, and BOUT should be shielded from the high-frequency terminals CLKR IN,

CLKG IN ,and CLKB IN and the input data terminals. GND traces should be placed on both sides of the ROUT,

GOUT, and BOUT traces on the PCB to the following signal processing stage. These output traces should

be as short as possible.

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