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ADC1113D125HN-C1 Arkusz danych(PDF) 10 Page - Integrated Device Technology |
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ADC1113D125HN-C1 Arkusz danych(HTML) 10 Page - Integrated Device Technology |
10 / 39 page ADC1113D125 4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 10 of 39 Integrated Device Technology ADC1113D125 Dual 11-bit ADC; serial JESD204A interface 10.2 Clock and digital output timing [1] Typical values measured at VDDA =3V, VDDD = 1.8 V, Tamb =25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA =3 V, VDDD = 1.8 V; VI (INAP, INBP) VI (INAM, INBM) = 1 dBFS; internal reference mode; 100 W differential applied to serial outputs; unless otherwise specified. 10.3 Serial output timing The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions are: • 3.125 Gbps data rate • Tamb =25°C • DC coupling with two different receiver common-mode voltages Table 7. Characteristics[1] Symbol Parameter Conditions Min Typ Max Unit Clock timing input: pins CLKP and CLKM fclk clock frequency 100 - 125 Msps tlat(data) data latency time - 14 - clock cycle clk clock duty cycle DCS_EN = logic 1 30 50 70 % DCS_EN = logic 0 45 50 55 % td(s) sampling delay time - 0.8 - ns twake wake-up time - 76 - s Fig 3. Eye diagram at 1 V receiver common-mode 005aaa088 |
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