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ADC1113S125 Arkusz danych(PDF) 11 Page - Integrated Device Technology |
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ADC1113S125 Arkusz danych(HTML) 11 Page - Integrated Device Technology |
11 / 36 page ADC1113S125 2 © IDT 2012. All rights reserved. Product data sheet Rev. 02 — 2 July 2012 11 of 36 Integrated Device Technology ADC1113S125 Single 11-bit ADC; serial JESD204A interface 10.4 SPI timing [1] Typical values measured at VDDA =3 V, VDDD(1V8) = 1.8 V, Tamb =25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA =3 V, VDDD(1V8) =1.8 V; Vi(INP) Vi(INM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified. Table 8. SPI timing characteristics[1] Symbol Parameter Conditions Min Typ Max Unit tw(SCLK) SCLK pulse width - 40 - ns tw(SCLKH) SCLK HIGH pulse width -16 - ns tw(SCLKL) SCLK LOW pulse width -16 - ns tsu set-up time data to SCLK HIGH -5 - ns CS to SCLK HIGH -5 - ns th hold time data to SCLK HIGH -2 - ns CS to SCLK HIGH22 -2 - ns fclk(max) maximum clock frequency -25 - MHz Fig 5. SPI timing tsu SDIO SCLK R/W W1 W0 A12 A11 D2 D1 D0 tsu th th tw(SCLK) 005aaa065 CS tw(SCLKL) tw(SCLKH) |
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