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TMP821DR Arkusz danych(PDF) 2 Page - Texas Instruments |
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TMP821DR Arkusz danych(HTML) 2 Page - Texas Instruments |
2 / 13 page www.ti.com PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 GND LD A1 A2 H– AL H+ V CC D PACKAGE (TOP VIEW) TMP821 SLDS152 – JANUARY 2008 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO. VCC 1 Power input (4 V to 28 V) H+ 2 Positive Hall input Speed indication AL 3 Note: May remain high for several hundred milliseconds after power-on. H– 4 Negative Hall input GND 5 Ground LD 6 Timing capacitor A1 7 Driver output A2 8 Driver output 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated |
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