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ADS1131 Arkusz danych(PDF) 5 Page - Texas Instruments |
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ADS1131 Arkusz danych(HTML) 5 Page - Texas Instruments |
5 / 20 page DVDD GND GND SPEED CAP CAP AINP AINN DRDY/DOUT SCLK PDWN AVDD PSW GND VREFP VREFN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ADS1131 www.ti.com SBAS449B – JULY 2009 – REVISED SEPTEMBER 2011 PIN CONFIGURATION D PACKAGE SO-16 (TOP VIEW) PIN DESCRIPTIONS ANALOG/DIGITAL NAME TERMINAL INPUT/OUTPUT DESCRIPTION DVDD 1 Digital Digital power supply GND 2 Supply Ground for digital and analog supplies GND 3 Supply Ground for digital and analog supplies Data rate select: SPEED DATA RATE SPEED 4 Digital input 0 10SPS 1 80SPS CAP 5 Analog Gain amplifier bypass capacitor connection CAP 6 Analog Gain amplifier bypass capacitor connection AINP 7 Analog input Positive analog input AINN 8 Analog input Negative analog input VREFN 9 Analog input Negative reference input VREFP 10 Analog input Positive reference input GND 11 Supply Ground for digital and analog supplies PSW 12 Analog Low-side power switch AVDD 13 Supply Analog power supply PDWN 14 Digital input Power-down: holding this pin low powers down the entire converter and resets the ADC. Serial clock: clock out data on the rising edge. Also used to initiate Standby mode. See the Standby SCLK 15 Digital input Mode section for more details. Dual-purpose output: DRDY/DOUT 16 Digital output Data ready: indicates valid data by going low. Data output: outputs data, MSB first, on the first rising edge of SCLK. Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 5 |
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