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TPS1110D Arkusz danych(PDF) 4 Page - Texas Instruments |
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TPS1110D Arkusz danych(HTML) 4 Page - Texas Instruments |
4 / 10 page TPS1110, TPS1110Y SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dynamic PARAMETER TEST CONDITIONS TPS1110 TPS1110Y UNIT PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT Qg Total gate charge 4.3 5.4 4.3 Qgs Gate-to-source charge VDS = – 6 V, VGS = – 6 V, See Figures 1 and 10 ID = – 3 A 0.66 0.83 0.66 nC Qgd Gate-to-drain charge 0.52 0.68 0.52 td(on) Turn-on delay time 5.8 8 5.8 ns td(off) Turn-off delay time VDD = – 6 V, RL = 6 Ω,ID = – 1 A, 22 29 22 ns tr Rise time DD RG = 6 Ω, L See Figure 2 D 22 29 22 tf Fall time 4.5 7 4.5 ns trr(SD) Source-to-drain reverse-recovery time VDS = – 6 V, di/dt = 100 A/ µs, ID = – 3 A 65 98 65 ns Qrr Total diode charge DS , µ , D 71 71 nC PARAMETER MEASUREMENT INFORMATION Qg –6 V VOLTAGE WAVEFORM Time Gate Voltage VGS 12-V Battery 0.2 µF 50 k Ω 0.3 µF Current Regulator DUT Same Type as DUT IG = – 50 µA IG Current- Sampling Resistor ID Current- Sampling Resistor VDD TEST CIRCUIT –6 V Qgs Qgd Figure 1. Gate-Charge Test Circuit and Waveform |
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