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SN74ACT8999DW Arkusz danych(PDF) 10 Page - Texas Instruments |
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SN74ACT8999DW Arkusz danych(HTML) 10 Page - Texas Instruments |
10 / 29 page SN54ACT8999, SN74ACT8999 SCANPATH SELECTORS WITH 8BIT BIDIRECTIONAL DATA BUSES SCANCONTROLLED IEEE STD 1149.1 (JTAG) TAP MULTIPLEXERS SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 control-register description The control register (CTLR) is a 13-bit serial register that controls the enable and select functions of the ’ACT8999. A reset operation forces all bits to a logic 0. The contents of the control register are latched and decoded during the Update-DR TAP state. The specific function of each bit is listed in Table 5. The enable and select functions of the control register bits are mapped as follows: Table 5. Control-Register Bit Mapping BIT VALUE FUNCTION 12 0 Configure counter to count up 12 1 Configure counter to count down 11 0 Do not stop counting when the count reaches 00000000 11 1 Stop counting when the count reaches 00000000 (count down only) 10 0 Configure DCO as an active-low output 10 1 Configure DCO as an active-high output 00 DCO = Inactive (level depends on CTLR bit 10) 9, 8 01 DCO = (IRERR • SRERR) 9, 8 10 DCO = CE, an internal logic 0 generated when the count is 00000000 (count down) or 11111111 (count up) 11 DCO = DCI 7 0 Do not mask IRERR and SRERR from DCO 7 1 Mask IRERR and SRERR from DCO 6 0 Configure DCO as an open-drain output 6 1 Configure DCO as a 3-state output 5 0 Disable DCO 5 1 Enable DCO 4 0 Configure DCI as an active-low input 4 1 Configure DCI as an active-high input 3 0 Enable DTCK, DTDO, and DTMS(1− 4) 3 1 Disable DTCK, DTDO, and DTMS(1− 4) 2 0 Disable ID(1− 8) 2 1 Enable ID(1− 8) 1 0 Disable RBC 1 1 Enable RBC 0 0 DTRST = TRST 0 1 DTRST = L Bit 12 − Up/Down This bit sets the count mode of the counter register (reset condition = count up). Bit 11 − Latch on Zero The counter register can be configured to stop counting when its value is 00000000 and ignore subsequent transitions on the counter clock, DCI. The latch-on-zero option is valid only in the count-down mode (reset condition = do not latch on zero). The value of this bit has no effect on the operation of the counter if CTLR bit 12 = 0. Bit 10 − DCO Polarity Select DCO can be configured as an active-low or active-high output (reset condition = active low). |
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