Zakładka z wyszukiwarką danych komponentów |
|
SN74ALS114A Arkusz danych(PDF) 1 Page - Texas Instruments |
|
SN74ALS114A Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 4 page SN54ALS114A, SN74ALS114A DUAL JK NEGATIVEEDGETRIGGERED FLIPFLOPS WITH PRESET,COMMON CLEAR,AND COMMON CLOCK SDAS201 − D2661, DECEMBER 1982 − REVISED MAY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 Copyright 1986, Texas Instruments Incorporated 5BASIC 1 • Fully Buffered to Offer Maximum isolation from External Disturbance • Package Options include Plastic Small Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs • Typical Maximum Clock Frequency 30 MHz • Typical Power Dissipation per Flip-Flop 6 mW • Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the Preset or Clear inputs sets or resets the outputs regardless of the levels of the other inputs. When Preset and Clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54ALS114A is characterized for operation over the full military temperature range of − 55 °C to 125 °C. The SN74ALS114A is characterized for operation from 0 °C to 70°C. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H LX X X L H L L X XXH† H† H H ↓ LL Q0 Q0 H H ↓ HL H L H H ↓ LH L H H H ↓ H H TOGGLE H H H X X Q0 Q0 † The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at Preset and Clear are near VIL maximum. Furthermore, this configuration is nonstable; that is, it will not persist when either Preset or Clear returns to its inactive (high) level. logic symbol‡ Pin numbers are for D, J, and N packages. 1Q 1Q 2Q 2Q 8 9 6 5 R 1K C1 1J S 12 2K 10 2PRE 13 CLK 11 2J 2 1K 1 CLR 3 1J 1PRE 4 1 2 3 4 5 6 7 14 13 12 11 10 9 8 CLR 1K 1J 1PRE 1Q 1Q GND VCC CLK 2K 2J 2PRE 2Q 2Q SN54ALS114A ...J PACKAGE SN74ALS114A ...D OR N PACKAGE (TOP VIEW) 3 2 1 20 19 910 11 12 13 4 5 6 7 8 18 17 16 15 14 2K NC 2J NC 2PRE 1J NC 1PRE NC 1Q SN54ALS114A . . . FK PACKAGE (TOP VIEW) NC−No internal connection ‡ This symbol is in accordance with ANSI/IEEE Std 911-1984 and IEC Publication 617-12. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
Podobny numer części - SN74ALS114A |
|
Podobny opis - SN74ALS114A |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |