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FAN21SV04 Arkusz danych(PDF) 3 Page - Fairchild Semiconductor

Numer części FAN21SV04
Szczegółowy opis  TinyBuck??4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
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Producent  FAIRCHILD [Fairchild Semiconductor]
Strona internetowa  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN21SV04 Arkusz danych(HTML) 3 Page - Fairchild Semiconductor

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© 2009 Fairchild Semiconductor Corporation
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FAN21SV04 • Rev. 1.0.3
3
Pin Configuration
Figure 3. MLP 5x6 mm Pin Configuration (Bottom View)
Pad / Pin Definitions
Pad / Pin
Name
Description
P1, 6-12
SW
Switching Node. Junction of high-side and low-side MOSFETs.
P2, 3-5
VIN
Power Conversion Input Voltage. Connect to the main input power source.
P3, 21-23
PGND
Power Ground. Power return and Q2 source.
1
BOOT
High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC has an
internal synchronous bootstrap diode to recharge the capacitor on this pin to 5 V_Reg when
SW is LOW.
2
VIN_Reg
Regulator Input Voltage. Input voltage to the internal regulator. Connect to input voltage
>6.5 V with 10
Ω resistor and a 1 µF bypass capacitor at the pin (see Figure 10).
13
PGOOD
Power-Good. An open-drain output that pulls LOW when the voltage on the FB pin is
outside the specified limits. PGOOD does not assert HIGH until the fault latch is enabled
(see Figure 31).
14
EN
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched-fault condition. This input has an internal pull-up. When a latched
fault occurs, EN is discharged by a current sink.
15
5V_Reg
5V Regulator Output. Internal regulator output that provides power for the IC’s logic and
analog circuitry. This pin should be connected to AGND through a >2.2 µf X5R/X7R
capacitor.
16
AGND
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
17
ILIM
Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the current-
limit trip threshold lower than the internal default setting.
18
RT
Switching Frequency and Master/Slave Set. Connecting a resistor (RT) to AGND sets the
switching frequency and configures the CLK pin as an output (master). Tying this pin to
5 V_Reg through a resistor configures the CLK signal as an input (slave) and establishes
the free-running switching frequency.
19
FB
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
20
COMP
Compensation. Error amplifier output. Connect the external compensation network
between this pin and FB.
24
CLK
Clock. Bi-directional signal pin, depending on master/slave configuration. When configured
as a master, this pin represents the clock output that connects directly to the slave(s) for
synchronizing with 180° phase shift.
25
RAMP
Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the internal ramp
amplitude and also provides voltage feedforward functionality.


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