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FAN48630UC315X Arkusz danych(PDF) 3 Page - Fairchild Semiconductor |
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FAN48630UC315X Arkusz danych(HTML) 3 Page - Fairchild Semiconductor |
3 / 15 page © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN48630 • Rev. 1.0.1 3 Pin Configuration AGND VIN VSEL PG AGND PGND SW VOUT EN B1 B2 C2 A1 A2 B3 A3 C3 D1 D2 D3 C1 A4 B4 C4 D4 BYP Figure 3. Top Through View (Bumps Down) Figure 4. Bottom View (Bumps Up) Pin Definitions Pin # Name Description A1 EN Enable. When this pin is HIGH, the circuit is enabled. A2 PG Power Good. This is an open-drain output. PG is actively pulled LOW if output falls out of regulation due to overload or if thermal protection threshold is exceeded. A3–A4 VIN Input Voltage. Connect to Li-Ion battery input power source. B1 VSEL Output Voltage Select. When boost is running, this pin can be used to select output voltage. B2, C2 D1 AGND Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. B3–B4 VOUT Output Voltage. Place COUT as close as possible to the device. C1 BYP Bypass. This pin can be used to activate Forced Bypass Mode. When this pin is LOW, the bypass switches (Q3 and Q1) are turned on and the IC is otherwise inactive. C3–C4 SW Switching Node. Connect to inductor. D2–D4 PGND Power Ground. This is the power return for the IC. The COUT bypass capacitor should be returned with the shortest path possible to these pins. |
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