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AD9250BCPZRL7-170 Arkusz danych(PDF) 1 Page - Analog Devices

Numer części AD9250BCPZRL7-170
Szczegółowy opis  14-Bit, 170 MSPS/250 MSPS, JESD204B,Dual Analog-to-Digital Converter
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Strona internetowa  http://www.analog.com
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AD9250BCPZRL7-170 Arkusz danych(HTML) 1 Page - Analog Devices

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14-Bit, 170 MSPS/250 MSPS, JESD204B,
Dual Analog-to-Digital Converter
Data Sheet
AD9250
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and
250 MSPS
Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz
AIN and 250 MSPS
Total power consumption: 711 mW at 250 MSPS
1.8 V supply voltages
Integer 1-to-8 input clock divider
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
User-configurable, built-in self-test (BIST) capability
APPLICATIONS
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
I/Q demodulation systems
Smart antenna systems
Electronic test and measurement equipment
Radar receivers
COMSEC radio architectures
IED detection/jamming systems
General-purpose software radios
Broadband data applications
FUNCTIONAL BLOCK DIAGRAM
CML, TX
OUTPUTS
JESD-204B
INTERFACE
HIGH
SPEED
SERIALIZERS
PIPELINE
14-BIT ADC
PIPELINE
14-BIT ADC
CMOS
DIGITAL
INPUT/
OUTPUT
CMOS
DIGITAL
INPUT/
OUTPUT
FAST
DETECT
CONTROL
REGISTERS
CLOCK
GENERATION
AVDD
VIN+A
SDIO SCLK
FDB
FDA
PDWN
SERDOUT1±
SERDOUT0±
CS
VIN–A
VIN+B
VCM
VIN–B
SYSREF±
SYNCINB±
CLK±
RFCLK
DRVDD
DVDD
AGND DGND DRGND
CMOS
DIGITAL
INPUT/OUTPUT
AD9250
RST
Figure 1.
PRODUCT HIGHLIGHTS
1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
2. The configurable JESD204B output block supports up to
5 Gbps per lane.
3. An on-chip, phase-locked loop (PLL) allows users to provide a
single ADC sampling clock; the PLL multiplies the ADC
sampling clock to produce the corresponding JESD204B
data rate clock.
4. Support for an optional RF clock input to ease system board
design.
5. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
6. Operation from a single 1.8 V power supply.
7. Standard serial port interface (SPI) that supports various
product features and functions such as controlling the clock
DCS, power-down, test modes, voltage reference mode, over
range fast detection, and serial output configuration.


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