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AD1848KP Arkusz danych(PDF) 7 Page - Analog Devices

Numer części AD1848KP
Szczegółowy opis  Parallel-Port 16-Bit SoundPort Stereo Codec
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AD1848KP Arkusz danych(HTML) 7 Page - Analog Devices

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AD1848K
REV. 0
–7–
PIN DESCRIPTION
Parallel Interface
Pin Name
PLCC
TQFP
I/O
Description
CDRQ
12
3
O
Capture Data Request. The assertion of this signal indicates that the Codec has a cap-
tured audio sample from the ADC ready for transfer. This signal will remain asserted un-
til all the bytes from the capture buffer have been transferred.
CDAK
11
2
I
Capture Data Acknowledge. The assertion of this active LO signal indicates that the RD
cycle occurring is a DMA read from the capture buffer.
PDRQ
14
5
O
Playback Data Request. The assertion of this signal indicates that the Codec is ready for
more DAC playback data. The signal will remain asserted until all the bytes needed for a
playback sample have been transferred.
PDAK
13
4
I
Playback Data Acknowledge. The assertion of this active LO signal indicates that the WR
cycle occurring is a DMA write to the playback buffer.
ADR1:0
9 & 10
1 & 64
I
Codec Addresses. These address pins are asserted by the Codec interface logic during a
control register/PIO access. The state of these address lines determine which register is
accessed.
RD
60
47
I
Read Command Strobe. This active LO signal defines a read cycle from the Codec. The
cycle may be a read from the control/PIO registers, or the cycles could be a read from the
Codec’s DMA sample registers.
WR
61
48
I
Write Command Strobe. This active LO signal indicates a write cycle to the Codec. The
cycle may be a write to the control/PIO registers, or the cycle could be a write to the
Codec’s DMA sample registers.
CS
59
46
I
AD1848K Chip Select. The Codec will not respond to any control/PIO cycle accesses
unless this active LO signal is LO. This signal is ignored during DMA transfers.
DATA7:0
3–6 &
52–55 &
I/O
Data Bus. These pins transfer data and control information between the Codec and the
65–68
58–61
host.
DBEN
63
50
O
Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI.
For control register/PIO cycles,
DBEN
= (WR or RD) and CS
For DMA cycles,
DBEN
= (WR or RD) and (PDAK or CDAK)
DBDIR
62
49
O
Data Bus Direction. This pin controls the direction of the data bus transceiver. HI
enables writes from the host to the AD1848K; LO enables reads from the AD1848K to
the host bus. This signal is normally HI.
For control register/PIO cycles,
DBDIR = RD and CS
For DMA cycles,
DBDIR = RD and (PDAK or CDAK)


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