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AD1852JRS Arkusz danych(PDF) 8 Page - Analog Devices

Numer części AD1852JRS
Szczegółowy opis  Stereo, 24-Bit, 192 kHz Multibit DAC
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD1852JRS Arkusz danych(HTML) 8 Page - Analog Devices

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AD1852
–8–
REV. 0
Note that the AD1852 is capable of a 32
× F
S BCLK frequency
“packed mode” where the MSB is left-justified to an L/
RCLK
transition, and the LSB is right-justified to the opposite L/
RCLK
transition. L/
RCLK is HI for the left channel, and LO for the
right channel. Data is valid on the rising edge of BLCK. Packed
mode can be used when the AD1852 is programmed in right-
justified or left-justified mode. Packed mode is shown is Figure 5.
Master Clock Autodivide Feature
The AD1852 has a circuit that autodetects the relationship
between master clock and the incoming serial data, and inter-
nally sets the correct divide ratio to run the interpolator and
modulator. The allowable frequencies for each mode are shown
above. Master clock should be synchronized with L/
RCLK but
phase relation between master clock and L/
RCLK is not critical.
D15
D14
D0
tCHD
tCCH
tCSU
tCCL
tCLL
tCLH
CDATA
CCLK
CLATCH
tCLSU
Figure 7. Serial Control Port Timing
Table II.
Nominal Input
Internal Sigma-
Chip Mode
Allowable Master Clock Frequencies
Sample Rate
Delta Clock Rate
INT8
× Mode
256
× F
S, 384
× F
S, 512
× F
S, 768
× F
S, 1024
× F
S
48 kHz
128
× F
S
INT4
× Mode
128
× F
S, 192
× F
S, 256
× F
S, 384
× F
S, 512
× F
S
96 kHz
64
× F
S
INT2
× Mode
64
× F
S, 96
× F
S, 128
× F
S, 192
× F
S, 256
× F
S
192 kHz
32
× F
S
SPI REGISTER DEFINITIONS
The SPI port allows flexible control of many chip parameters. It is
organized around three registers; a LEFT-CHANNEL VOLUME
register, a RIGHT-CHANNEL VOLUME register, and a
CONTROL register. Each WRITE operation to the AD1852
SPI control port requires 16 bits of serial data in MSB-first format.
The bottom two bits are used to select one of three registers,
and the top 14 bits are then written to that register. This allows
a write to one of the three registers in a single 16-bit transaction.
The SPI CCLK signal is used to clock in the data. The incom-
ing data should change on the falling edge of this signal. At the
end of the 16 CCLK periods, the CLATCH signal should rise
to clock the data internally into the AD1852.


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