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AD1853 Arkusz danych(PDF) 7 Page - Analog Devices

Numer części AD1853
Szczegółowy opis  Stereo, 24-Bit, 192 kHz, Multibit DAC
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Strona internetowa  http://www.analog.com
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AD1853 Arkusz danych(HTML) 7 Page - Analog Devices

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REV. A
AD1853
–7–
OPERATING FEATURES
Serial Data Input Port
The AD1853’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The serial mode is
set by using either the external mode pins (IDPM0 Pin 21 and
IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI
control register. To control the serial mode using the external
mode pins, the SPI mode select bits should be set to zero
(default at power-up). To control the serial mode using the SPI
mode select bits, the external mode control pins should be
grounded.
In all modes except for the right-justified mode, the serial port
will accept an arbitrary number of bits up to a limit of 24 (extra
bits will not cause an error, but they will be truncated inter-
nally). In the right-justified mode, control register Bits 8 and 9
are used to set the word length to 16, 20, or 24 bits. The default
on power-up is 24-bit mode. When the SPI Control Port is not
being used, the SPI pins (3, 4 and 5) should be tied LO.
Serial Data Input Mode
The AD1853 uses two multiplexed input pins to control the
mode configuration of the input data port mode.
Table I. Serial Data Input Modes
IDPM1
IDPM0
(Pin 20)
(Pin 21)
Serial Data Input Format
0
0
Right Justified (24 Bits) Default
01
I
2S-Compatible
1
0
Left Justified
1
1
DSP
Figure 1 shows the right-justified mode. LRCLK is HI for the
left channel, LO for the right channel. Data is valid on the rising
edge of BCLK.
In normal operation, there are 64-bit clocks per frame (or 32
per half-frame). When the SPI word length control bits (Bits 8
and 9 in the control register) are set to 24 bits (0:0), the serial
port will begin to accept data starting at the 8th bit clock pulse
after the L/RCLK transition. When the word length control bits
are set to 20-bit mode, data is accepted starting at the 12th bit
clock position. In 16-bit mode, data is accepted starting at the
16th-bit clock position. These delays are independent of the
number of bit clocks per frame, and therefore other data formats
are possible using the delay values described above. For detailed
timing, see Figure 6.
Figure 2 shows the I
2S mode. L/RCLK is LO for the left chan-
nel, and HI for the right channel. Data is valid on the rising
edge of BCLK. The MSB is left-justified to an L/RCLK transi-
tion but with a single BCLK period delay. The I
2S mode can be
used to accept any number of bits up to 24.
Figure 3 shows the left-justified mode. L/RCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left-justified to an L/RCLK
transition, with no MSB delay. The left-justified mode can
accept any word length up to 24 bits.
Figure 4 shows the DSP serial port mode. L/RCLK must pulse
HI for at least one bit clock period before the MSB of the left
channel is valid, and L/RCLK must pulse HI again for at least
one bit clock period before the MSB of the right channel is
valid. Data is valid on the falling edge of BCLK. The DSP serial
port mode can be used with any word length up to 24 bits.
tDLS
BCLK
L/RCLK
SDATA
LEFT-JUSTIFIED
MODE
SDATA
RIGHT-JUSTIFIED
MODE
LSB
SDATA
I2S-JUSTIFIED
MODE
tDBH
tDBP
tDBL
tDDS
MSB
MSB-1
tDDH
tDDS
MSB
tDDH
tDDS
tDDS
tDDH
tDDH
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 6. Serial Data Port Timing


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