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AD1879JD Arkusz danych(PDF) 8 Page - Analog Devices |
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AD1879JD Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 16 page AD1878/AD1879 REV. 0 –8– RIGHT INPUT NE5532 OR OP-275 100pF .1µF 5.76k Ω 100pF V CC V SS 249k Ω 100k Ω 249k Ω V SS .1µF .0047 µF NPO .01µF NPO .01µF NPO NE5532 OR OP-275 VINR– VINR+ VINL+ VINL– 12 13 16 17 REFR REFL 10µF 14 .1µF AD1878/79 LEFT INPUT 100pF 100pF V CC .1µF .0047 µF NPO .01µF NPO NE5532 OR OP-275 .1µF V CC V SS .1µF .01µF NPO 10µF 15 5.62k Ω 5.62k Ω 5.62k Ω 5.62k Ω 5.49k Ω 51 Ω 51 Ω 200 Ω 249k Ω 5.62k Ω 100k Ω 5.36k Ω 200 Ω 51 Ω 51 Ω 5.62k Ω 5.62k Ω 5.62k Ω 249k Ω 5.90k Ω Figure 2. AD1878/AD1879 Recommended Input Structure V CC AGND V SS V DD DGND 0.1µF 22µF 7805 IN OUT GND +5V ANALOG –5V ANALOG +5V DIGITAL +12V < V CC < +18V –12V > V SS > – 18V 0.1µF 22µF 0.1µF 22µF 7905 IN OUT GND 0.1µF 10µF 0.1µF 10µF Figure 3. AD1878/AD1879 Recommended Power Condi- tioning Circuit (If ±5 V Supplies Are Not Already Available) The trim potentiometers shown in Figure 2 connecting the minus (–) inputs of the driving op amps permit trimming out dc offset, if desired. Note that the driving op amp feedback resistors are all slightly different values. These values produce a slight differential gain imbalance and were derived empirically to minimize second harmonic distortion on average and produce the best overall THD without part-by-part trimming. Replacing one of these feedback resistors in each channel with a trim potentiometer allows trimming the differential gain imbalance for part-by-part optimal performance. We have done this in the lab by parallel- ing 100 k Ω trim potentiometers around the 5.49 kΩ and 5.36 k Ω input feedback resistors for the V IN plus (+) signals that can be found in Figure 2. By trimming gain imbalance, sec- ond harmonic distortion can always be eliminated. In “Specifi- cations,” a distinction is drawn between trimmed and untrimmed signal-to (noise + distortion) and trimmed and untrimmed total harmonic distortion. The untrimmed specifications are tested to the input structure shown in Figure 2. The trimmed specifica- tions are based on a part-by-part trim of this differential gain to eliminate the second harmonic. The input circuit of Figure 2 could be implemented with a single pair of operational amplifiers per channel, one inverting and one noninverting. The recommended architecture shown in Figure 2 using three inverting op amps per channel provides iso- lation of the op amp inputs from charge dumped back from the AD1878/AD1879’s input capacitors when these large capacitors switch. The performance from a two op amp per channel input structure is not quite as good as the structure recommended, but it is close and may be adequate in many applications. Layout and Decoupling Considerations Obtaining the best possible performance from a state-of-the-art data converter like the AD1878/AD1879 requires close atten- tion to board layout. From extensive experimentation, we have discovered principles that produce typical values of 103 dB dy- namic range and 98 dB S/(THD+N) in your system. Schematics of our AD1878/AD1879 Evaluation Board, which implements these recommendations, are available from Analog Devices. The principles and their rationales are listed below in descend- ing order of importance. The first two pertain to bypassing and are illustrated in Figure 4. AD1878/ 79 AV SS 1 AV SS 1 AV DD 1 AGND AGND 10µF –5V ANALOG +5V ANALOG 10µF 0.1µF +5V DIGITAL 10µF 0.1µF +5V DIGITAL AV SS 2 AV DD 2 DV DD DGND DGND DV DD –5V ANALOG +5V ANALOG +5V DIGITAL OSCILLATOR 0.1µF 26 CLKIN 10µF 10µF 821 19 10 18 920 5 6 23 22 Figure 4. AD1878/AD1879 Recommended Bypassing and Oscillator Circuits • The digital bypassing of the AD1878/AD1879 is the most critical item on the board layout. There are two pairs of digi- tal supply pins of the part, each pair on opposite sides (Pins 5 and 6 and Pins 22 and 23). The user should tie a bypass ca- pacitor set (0.1 µF ceramic and 10 µF tantalum) on EACH pair of supply pins as close to the pins as possible. The traces between these package pins and the capacitors should be as short and as wide as possible. This will prevent digital supply current transients from being inductively transmitted to the inputs of the part. • The analog input bypassing is the second most critical item. Use 0.01 µF NPO ceramic capacitors from each input pin to the analog ground plane, with a clear ground path from the bypass capacitor to the AGND pin on the same side of the package (Pins 10 and 18). The trace between this package pin and the capacitor should be as short and as wide as pos- sible. A 0.0047 µF NPO ceramic capacitor should be placed |
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