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AD538 Arkusz danych(PDF) 9 Page - Analog Devices |
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AD538 Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 11 page AD538 –9– REV. C ANALOG COMPUTATION OF POWERS AND ROOTS It is often necessary to raise the quotient of two input signals to a power or take a root. This could be squaring, cubing, square- rooting or exponentiation to some noninteger power. Examples include power series generation. With the AD538, only one or two external resistors are required to set ANY desired power, over the range of 0.2 to 5. Raising the basic quantity VZ /VX to a power greater than one requires that the gain of the AD538’s log ratio subtractor be increased, via an external resistor between pins A and D. Similarly, a voltage divider that attenuates the log ratio output between points B and C will program the power to a value less than one. 312 18 17 2 10 15 8 VY ( )m VZ VREF RA VO VZ VY VREF VX B CAD RA = 196 M –1 RB = RC 200 POWERS m RA 2 196 3 97.6 4 64.9 5 48.7 312 2 10 15 8 VY ( )m VZ VREF VO VZ VY VREF VX BC RB RC ROOTS m RB RC 1/2 100 100 1/3 100 49.9 1/4 150 49.9 1/5 162 40.2 RB RC = –1 1 M Figure 15. Basic Configurations and Transfer Functions for the AD538 +15V –15V D1 IN4148 VOUT = 1V VIN 1V * * RC 100 RB 100 VOUT 7 1 8 6 4 2 3 +VS IN4148 IN4148 AD OP-07 OR AD611 (VOS TAP TO –VS) –VS 20k 5k 20k OPTIONAL ABSOLUTE VALUE SECTION 10k VIN +2V 1k 1k 100 SCALE FACTOR TRIM RATIO MATCH 1% METAL FILM RESISTORS FOR BEST ACCURACY * 25k 25k LOG RATIO 100 25k 25k ANTILOG LOG OUTPUT 100 AD538 INTERNAL VOLTAGE REFERENCE I VO IZ VZ B +10V IY A D IX VX C PWR GND SIGNAL GND VY 118 17 16 15 14 13 12 11 10 2 3 4 5 6 7 8 9 +2V VOS 20k Figure 16. Square Root Circuit SQUARE ROOT OPERATION The explicit square root circuit of Figure 16 illustrates a precise method for performing a real-time square root computation. For added flexibility and accuracy, this circuit has a scale factor adjustment. The actual square rooting operation is performed in this circuit by raising the quantity VZ /VX to the one-half power via the resistor divider network consisting of resistors RB and RC. For maximum linearity, the two resistors should be 1% (or better) ratio-matched metal film types. One volt scaling is achieved by dividing-down the 2 V reference and applying approximately 1 V to both the VY and VX inputs. In this circuit, the VX input is intentionally set low, to about 0.95 V, so that the VY input can be adjusted high, permitting a ±5% scale factor trim. Using this trim scheme, the output volt- age will be within ±3 mV ± 0.2% of the ideal value over a 10 V to 1 mV input range (80 dB). For a decreased input dynamic range of 10 mV to 10 V (60 dB) the error is even less; here the output will be within ±2 mV ± 0.2% of the ideal value. The bandwidth of the AD538 square root circuit is approximately 280 kHz with a 1 V p-p sine wave with a +2 V dc offset. This basic circuit may also be used to compute the cube, fourth or fifth roots of an input waveform. All that is required for a given root is that the correct ratio of resistors, RC and RB, be selected such that their sum is between 150 Ω and 200 Ω. The optional absolute value circuit shown preceding the AD538 allows the use of bipolar input voltages. Only one op amp is required for the absolute value function because the IZ input of the AD538 functions as a summing junction. If it is necessary to preserve the sign of the input voltage, the polarity of the op amp output may be sensed and used after the computation to switch the sign bit of a D.V.M. chip. |
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Podobny opis - AD538 |
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