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AD537JH Arkusz danych(PDF) 4 Page - Analog Devices |
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AD537JH Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 8 page AD537 REV. C –4– The –VIN, +VIN and IIN pins should not be driven more than 300 mV below –VS. This would cause internal junctions to con- duct, possibly damaging the IC. The AD537 can be protected from “below –VS” inputs by a Schottky diode, CR1 (HP5082- 2811) as shown in Figure 3. It is also desirable not to drive +VIN, –VIN and IIN above +VS. In operation, the converter will become very nonlinear for inputs above (+VS – 3.5 V). Control currents above 2 mA will also cause nonlinearity. The 80 dB dynamic range of the AD537 guarantees operation from a control current of 1 mA (nominal FS) down to 100 nA (equivalent to 1 mV to 10 V FS). Below 100 nA improper op- eration of the oscillator may result, causing a false indication of input amplitude. In many cases this might be due to short-lived noise spikes which become added to the input. For example, when scaled to accept a FS input of 1 V, the –80 dB level is only 100 µV, so when the mean input is only 60 dB below FS (1 mV), noise spikes of 0.9 mV are sufficient to cause momen- tary malfunction. This effect can be minimized by using a simple low-pass filter ahead of the converter and a guard ring around the IIN or –VIN pins. For a FS of 10 kHz a single-pole filter with a time-constant of 100 ms (Figure 2) will be suitable, but the optimum configu- ration will depend on the application and type of signal process- ing. Noise spikes are only likely to be a cause of error when the input current remains near its minimum value for long periods of time; above 100 nA (1 mV) full integration of additive input noise occurs. The AD537 is somewhat susceptible to interference from other signals. The most sensitive nodes (besides the inputs) are the capacitor terminals and the SYNC pin. The timing capacitor should be located as close as possible to the AD537 to minimize signal pickup in the leads. In some cases, guard rings or shield- ing may be required. The SYNC pin should be decoupled through a 0.005 µF (or larger) capacitor to Pin 13 (+VS). This minimizes the possibility that the AD537 will attempt to syn- chronize to a spurious signal. This precaution is unnecessary on the metal can package since the SYNC function is not brought out to a package pin and is thus not susceptible to pickup. DECOUPLING It is good engineering practice to use bypass capacitors on the supply-voltage pins and to insert small-valued resistors (10 Ω to 100 Ω) in the supply lines to provide a measure of decoupling between the various circuits in a system. Ceramic capacitors of 0.1 µF to 1.0 µF should be applied between the supply-voltage pins and analog signal ground for proper bypassing on the AD537. A decoupling capacitor may also be useful from +VS to SYNC in those applications where very low cycle-to-cycle period varia- tion (jitter) is demanded. By placing a capacitor across +VS and SYNC this noise is reduced. On the 10 kHz FS range, a 6.8 µF capacitor reduces the jitter to one in 20,000 which adequate for most applications. A tantalum capacitor should be used to avoid errors due to dc leakage. In some cases the signal may be in the form of a negative cur- rent source. This can be handled in a similar way to a negative input voltage. However, the scaling resistor is no longer re- quired, eliminating the capability of trimming full scale in this fashion. Since it will usually be impractical to vary the capaci- tance, an alternative calibration scheme is needed. This is shown in Figure 3. A resistor-potentiometer connected from the VR output to –VS will alter the internal operating conditions in a predictable way, providing the necessary adjustment range. With the values shown, a range of ±4% is available; a larger range can be attained by reducing R1. This technique does not degrade the temperature-coefficient of the converter, and the linearity will be as for negative input voltages. The minimum supply voltage may be used. Unless it is required to set the input node at exactly ground potential, no offset adjustment is needed. The capacitor C is se- lected to be 5% below the nominal value; with R2 in its midposition the output frequency is given by: f = I 10.5 × C where f is in kHz, I is in mA and C is in µF. For example, for a FS frequency of 10 kHz at a FS input of 1 mA, C = 9500 pF. Calibration is effected by applying the full-scale input and ad- justing R2 for the correct reading. This alternative adjustment scheme may also be used when it is desired to present an exact input resistance in the negative volt- age mode. The scaling relationship is then f = V REXACT × 1 10.5 C The calibration procedure is then similar to that used for posi- tive input voltages, except that the scale adjustment is by means of R2. 1 2 14 13 5 6 7 10 9 8 3 4 12 11 AD537 R1 27k R2 200k C +VS IIN 10C f = OUTPUT VLOGIC CAP –VS VOS VOS LOGIC GND I V ADJ. SCALE DEC/SYN VTEMP VREF BUF DRIVER CURR- TO-FREQ CONV PRECISION VOLTAGE REFERENCE VT VR IIN Figure 3. Scale Adjustment for Current Inputs INPUT PROTECTION The AD537 was designed to be used with a minimum of addi- tional hardware. However, the successful application of a preci- sion IC involves a good understanding of possible pitfalls and the use of suitable precautions. |
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